linux-kernel - Re: [v2 03/10] drivers/perf: riscv: Read upper bits of a firmware counter

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Message-ID: <CAAhSdy3HgqPVCjnie-TtOC5uRWVXoZMRAKigvKK1+z0b7VHA2w@mail.gmail.com>
Date: Sat, 30 Dec 2023 13:25:59 +0530
From: Anup Patel <anup@...infault.org>
To: Atish Patra <atishp@...osinc.com>
Cc: linux-kernel@...r.kernel.org, Palmer Dabbelt <palmer@...osinc.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alexghiti@...osinc.com>, 
	Andrew Jones <ajones@...tanamicro.com>, Atish Patra <atishp@...shpatra.org>, 
	Conor Dooley <conor.dooley@...rochip.com>, Guo Ren <guoren@...nel.org>, 
	Heiko Stuebner <heiko@...ech.de>, kvm-riscv@...ts.infradead.org, kvm@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, Mark Rutland <mark.rutland@....com>, 
	Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Will Deacon <will@...nel.org>
Subject: Re: [v2 03/10] drivers/perf: riscv: Read upper bits of a firmware counter

On Sat, Dec 30, 2023 at 3:20 AM Atish Patra <atishp@...osinc.com> wrote:
>
> SBI v2.0 introduced a explicit function to read the upper 32 bits
> for any firmwar counter width that is longer than 32bits.
> This is only applicable for RV32 where firmware counter can be
> 64 bit.
>
> Acked-by: Palmer Dabbelt <palmer@...osinc.com>
> Signed-off-by: Atish Patra <atishp@...osinc.com>

LGTM.

Reviewed-by: Anup Patel <anup@...infault.org>

Regards,
Anup

> ---
>  drivers/perf/riscv_pmu_sbi.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 16acd4dcdb96..646604f8c0a5 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -35,6 +35,8 @@
>  PMU_FORMAT_ATTR(event, "config:0-47");
>  PMU_FORMAT_ATTR(firmware, "config:63");
>
> +static bool sbi_v2_available;
> +
>  static struct attribute *riscv_arch_formats_attr[] = {
>         &format_attr_event.attr,
>         &format_attr_firmware.attr,
> @@ -488,16 +490,23 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event)
>         struct hw_perf_event *hwc = &event->hw;
>         int idx = hwc->idx;
>         struct sbiret ret;
> -       union sbi_pmu_ctr_info info;
>         u64 val = 0;
> +       union sbi_pmu_ctr_info info = pmu_ctr_list[idx];
>
>         if (pmu_sbi_is_fw_event(event)) {
>                 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
>                                 hwc->idx, 0, 0, 0, 0, 0);
> -               if (!ret.error)
> -                       val = ret.value;
> +               if (ret.error)
> +                       return val;
> +
> +               val = ret.value;
> +               if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) {
> +                       ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI,
> +                                       hwc->idx, 0, 0, 0, 0, 0);
> +                       if (!ret.error)
> +                               val |= ((u64)ret.value << 32);
> +               }
>         } else {
> -               info = pmu_ctr_list[idx];
>                 val = riscv_pmu_ctr_read_csr(info.csr);
>                 if (IS_ENABLED(CONFIG_32BIT))
>                         val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val;
> @@ -1108,6 +1117,9 @@ static int __init pmu_sbi_devinit(void)
>                 return 0;
>         }
>
> +       if (sbi_spec_version >= sbi_mk_version(2, 0))
> +               sbi_v2_available = true;
> +
>         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
>                                       "perf/riscv/pmu:starting",
>                                       pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
> --
> 2.34.1
>