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Message-ID: <CAA8EJpqF=3n8vUrEzrGGLc4JtQ-s4EcOOr_NKC0rknwE0tuShw@mail.gmail.com>
Date: Tue, 2 Jan 2024 14:05:09 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Luca Weiss <luca@...tu.xyz>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: clock: qcom,hfpll: Convert to YAML
On Sun, 31 Dec 2023 at 16:49, Luca Weiss <luca@...tu.xyz> wrote:
>
> Convert the .txt documentation to .yaml.
>
> Take the liberty to change the compatibles for ipq8064, apq8064, msm8974
> and msm8960 to follow the updated naming schema. These compatibles are
> not used upstream yet.
>
> Also add a compatible for QCS404 since that SoC upstream already uses
> qcom,hfpll compatible but without an SoC-specific string.
>
> Signed-off-by: Luca Weiss <luca@...tu.xyz>
> ---
> .../devicetree/bindings/clock/qcom,hfpll.txt | 63 -----------------
> .../devicetree/bindings/clock/qcom,hfpll.yaml | 82 ++++++++++++++++++++++
> 2 files changed, 82 insertions(+), 63 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
> deleted file mode 100644
> index 5769cbbe76be..000000000000
> --- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -High-Frequency PLL (HFPLL)
> -
> -PROPERTIES
> -
> -- compatible:
> - Usage: required
> - Value type: <string>:
> - shall contain only one of the following. The generic
> - compatible "qcom,hfpll" should be also included.
> -
> - "qcom,hfpll-ipq8064", "qcom,hfpll"
> - "qcom,hfpll-apq8064", "qcom,hfpll"
> - "qcom,hfpll-msm8974", "qcom,hfpll"
> - "qcom,hfpll-msm8960", "qcom,hfpll"
> - "qcom,msm8976-hfpll-a53", "qcom,hfpll"
> - "qcom,msm8976-hfpll-a72", "qcom,hfpll"
> - "qcom,msm8976-hfpll-cci", "qcom,hfpll"
> -
> -- reg:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: address and size of HPLL registers. An optional second
> - element specifies the address and size of the alias
> - register region.
> -
> -- clocks:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: reference to the xo clock.
> -
> -- clock-names:
> - Usage: required
> - Value type: <stringlist>
> - Definition: must be "xo".
> -
> -- clock-output-names:
> - Usage: required
> - Value type: <string>
> - Definition: Name of the PLL. Typically hfpllX where X is a CPU number
> - starting at 0. Otherwise hfpll_Y where Y is more specific
> - such as "l2".
> -
> -Example:
> -
> -1) An HFPLL for the L2 cache.
> -
> - clock-controller@...16000 {
> - compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
> - reg = <0xf9016000 0x30>;
> - clocks = <&xo_board>;
> - clock-names = "xo";
> - clock-output-names = "hfpll_l2";
> - };
> -
> -2) An HFPLL for CPU0. This HFPLL has the alias register region.
> -
> - clock-controller@...8a000 {
> - compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
> - reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
> - clocks = <&xo_board>;
> - clock-names = "xo";
> - clock-output-names = "hfpll0";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml b/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
> new file mode 100644
> index 000000000000..2cb4098012bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm High-Frequency PLL
> +
> +maintainers:
> + - Bjorn Andersson <andersson@...nel.org>
> +
> +description:
> + The HFPLL is used as CPU PLL on various Qualcomm SoCs.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,apq8064-hfpll
> + - qcom,ipq8064-hfpll
> + - qcom,msm8960-hfpll
I think we should drop these entries. On msm8960 / apq8064 / ipq8064
the HFPLLs are a part of GCC, so there is no need for a separate
compat entry.
> + - qcom,msm8974-hfpll
This one is good, the HFPLL is separate, next to the acc / saw
> + - qcom,msm8976-hfpll-a53
> + - qcom,msm8976-hfpll-a72
> + - qcom,msm8976-hfpll-cci
Ok.
> + - qcom,qcs404-hfpll
> + - const: qcom,hfpll
> +
> + reg:
> + items:
> + - description: Base address and size of the register region
> + - description: Optional base address and size of the alias register region
> + minItems: 1
> +
> + '#clock-cells':
> + const: 0
> +
> + clocks:
> + items:
> + - description: board XO clock
> +
> + clock-names:
> + items:
> + - const: xo
> +
> + clock-output-names:
> + description:
> + Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
> + Otherwise hfpll_Y where Y is more specific such as "l2".
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> + - clocks
> + - clock-names
> + - clock-output-names
> +
> +additionalProperties: false
> +
> +examples:
> + # Example 1 - HFPLL for L2 cache
> + - |
> + clock-controller@...16000 {
> + compatible = "qcom,ipq8064-hfpll", "qcom,hfpll";
> + reg = <0xf9016000 0x30>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> + clock-output-names = "hfpll_l2";
> + #clock-cells = <0>;
> + };
> + # Example 2 - HFPLL for CPU0
> + - |
> + clock-controller@...8a000 {
> + compatible = "qcom,ipq8064-hfpll", "qcom,hfpll";
> + reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> + clock-output-names = "hfpll0";
> + #clock-cells = <0>;
> + };
>
> --
> 2.43.0
>
>
--
With best wishes
Dmitry
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