linux-kernel - Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature

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Message-ID: <ZZXE1WoXaAdkrH8A@LeoBras>
Date: Wed,  3 Jan 2024 17:34:29 -0300
From: Leonardo Bras <leobras@...hat.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: Leonardo Bras <leobras@...hat.com>,
	guoren@...nel.org,
	paul.walmsley@...ive.com,
	palmer@...belt.com,
	panqinglin2020@...as.ac.cn,
	bjorn@...osinc.com,
	conor.dooley@...rochip.com,
	peterz@...radead.org,
	keescook@...omium.org,
	wuwei2016@...as.ac.cn,
	xiaoguang.xing@...hgo.com,
	chao.wei@...hgo.com,
	unicorn_wang@...look.com,
	uwu@...nowy.me,
	jszhang@...nel.org,
	wefu@...hat.com,
	atishp@...shpatra.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature

On Wed, Jan 03, 2024 at 08:48:12PM +0100, Andrew Jones wrote:
> On Sun, Dec 31, 2023 at 03:29:51AM -0500, guoren@...nel.org wrote:
> ...
> > +#define CBO_PREFETCH_I(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(0),		\
> > +	       SIMM12(offset), RS1(base))
> > +
> > +#define CBO_PREFETCH_R(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(1),		\
> > +	       SIMM12(offset), RS1(base))
> > +
> > +#define CBO_PREFETCH_W(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),		\
> > +	       SIMM12(offset), RS1(base))
> 
> These should just be named
> 
>  PREFETCH_I
>  PREFETCH_R
>  PREFETCH_W
> 
> without the CBO_ prefix. The other CMO instructions we've added have the
> CBO_ prefix because their actual instruction names are e.g. cbo.zero,
> but the prefix instructions are not named that way.
> 
> Thanks,
> drew
> 

Sure, that's ok this way :)