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Message-ID: <365d76a4-db05-40ac-a453-fb7e8b6db423@quicinc.com>
Date: Wed, 3 Jan 2024 21:06:10 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<andrew@...n.ch>, <hkallweit1@...il.com>, <linux@...linux.org.uk>,
<robert.marko@...tura.hr>
CC: <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_srichara@...cinc.com>
Subject: Re: [PATCH v4 3/5] net: mdio: ipq4019: configure CMN PLL clock for
ipq5332
On 1/3/2024 5:50 PM, Bryan O'Donoghue wrote:
> On 25/12/2023 08:44, Luo Jie wrote:
>> The reference clock of CMN PLL block is selectable, the internal
>> 48MHZ is used by default.
>>
>> The output clock of CMN PLL block is for providing the clock
>> source of ethernet device(such as qca8084), there are 1 * 25MHZ
>> and 3 * 50MHZ output clocks available for the ethernet devices.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>> drivers/net/mdio/mdio-ipq4019.c | 129 +++++++++++++++++++++++++++++++-
>> 1 file changed, 128 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/mdio/mdio-ipq4019.c
>> b/drivers/net/mdio/mdio-ipq4019.c
>> index e24b0e688b10..e4862ac02026 100644
>> --- a/drivers/net/mdio/mdio-ipq4019.c
>> +++ b/drivers/net/mdio/mdio-ipq4019.c
>> @@ -44,6 +44,17 @@
>> /* Maximum SOC PCS(uniphy) number on IPQ platform */
>> #define ETH_LDO_RDY_CNT 3
>> +#define CMN_PLL_REFERENCE_SOURCE_SEL 0x28
>> +#define CMN_PLL_REFCLK_SOURCE_DIV GENMASK(9, 8)
>> +
>> +#define CMN_PLL_REFERENCE_CLOCK 0x784
>> +#define CMN_PLL_REFCLK_EXTERNAL BIT(9)
>> +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4)
>> +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0)
>> +
>> +#define CMN_PLL_POWER_ON_AND_RESET 0x780
>> +#define CMN_ANA_EN_SW_RSTN BIT(6)
>> +
>> enum mdio_clk_id {
>> MDIO_CLK_MDIO_AHB,
>> MDIO_CLK_UNIPHY0_AHB,
>> @@ -55,6 +66,7 @@ enum mdio_clk_id {
>> struct ipq4019_mdio_data {
>> void __iomem *membase;
>> + void __iomem *cmn_membase;
>> void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT];
>> struct clk *clk[MDIO_CLK_CNT];
>> };
>> @@ -227,12 +239,116 @@ static int ipq4019_mdio_write_c22(struct
>> mii_bus *bus, int mii_id, int regnum,
>> return 0;
>> }
>> +/* For the CMN PLL block, the reference clock can be configured
>> according to
>> + * the device tree property "qcom,cmn-ref-clock-frequency", the
>> internal 48MHZ
>> + * is used by default.
>> + *
>> + * The output clock of CMN PLL block is provided to the ethernet
>> devices,
>> + * threre are 4 CMN PLL output clocks (1*25MHZ + 3*50MHZ) enabled by
>> default.
>> + *
>> + * Such as the output 50M clock for the qca8084 ethernet PHY.
>> + */
>> +static int ipq_cmn_clock_config(struct mii_bus *bus)
>> +{
>> + struct ipq4019_mdio_data *priv;
>> + u32 reg_val, src_sel, ref_clk;
>> + int ret;
>> +
>> + priv = bus->priv;
>> + if (priv->cmn_membase) {
>
> if (!priv->cnm_membase)
> return 0;
>
> then move the indentation here one tab left.
>
Ok, will update this, Thanks.
> ---
> bod
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