linux-kernel - Re: [PATCH V2 2/3] riscv: Add ARCH_HAS

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Message-ID: <ZZWvtFaF5KPLt8Aw@LeoBras>
Date: Wed,  3 Jan 2024 16:04:20 -0300
From: Leonardo Bras <leobras@...hat.com>
To: Guo Ren <guoren@...nel.org>
Cc: Leonardo Bras <leobras@...hat.com>,
	paul.walmsley@...ive.com,
	palmer@...belt.com,
	panqinglin2020@...as.ac.cn,
	bjorn@...osinc.com,
	conor.dooley@...rochip.com,
	peterz@...radead.org,
	keescook@...omium.org,
	wuwei2016@...as.ac.cn,
	xiaoguang.xing@...hgo.com,
	chao.wei@...hgo.com,
	unicorn_wang@...look.com,
	uwu@...nowy.me,
	jszhang@...nel.org,
	wefu@...hat.com,
	atishp@...shpatra.org,
	ajones@...tanamicro.com,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop

On Mon, Jan 01, 2024 at 10:29:21AM +0800, Guo Ren wrote:
> On Sun, Dec 31, 2023 at 4:30 PM <guoren@...nel.org> wrote:
> >
> > From: Guo Ren <guoren@...ux.alibaba.com>
> >
> > Enable Linux prefetchw primitive with Zibop cpufeature, which preloads
> > cache line into L1 cache for the next write operation.
> >
> > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@...nel.org>
> > ---
> >  arch/riscv/include/asm/processor.h | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > index f19f861cda54..8d3a2ab37678 100644
> > --- a/arch/riscv/include/asm/processor.h
> > +++ b/arch/riscv/include/asm/processor.h
> > @@ -13,6 +13,9 @@
> >  #include <vdso/processor.h>
> >
> >  #include <asm/ptrace.h>
> > +#include <asm/insn-def.h>
> > +#include <asm/alternative-macros.h>
> > +#include <asm/hwcap.h>
> >
> >  #ifdef CONFIG_64BIT
> >  #define DEFAULT_MAP_WINDOW     (UL(1) << (MMAP_VA_BITS - 1))
> > @@ -106,6 +109,19 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
> >  #define KSTK_EIP(tsk)          (task_pt_regs(tsk)->epc)
> >  #define KSTK_ESP(tsk)          (task_pt_regs(tsk)->sp)
> >
> > +#ifdef CONFIG_RISCV_ISA_ZICBOP
> > +#define ARCH_HAS_PREFETCHW
> > +
> > +#define PREFETCHW_ASM(x)                                               \
> > +       ALTERNATIVE(__nops(1), CBO_PREFETCH_W(x, 0), 0,                 \
> > +                   RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)
> The PREFETCHW_ASM(x) definition should be out of "ifdef
> CONFIG_RISCV_ISA_ZICBOP... #endif", because xchg_small may use this
> macro without CONFIG_RISCV_ISA_ZICBOP.
> 

Agree :)

> > +
> > +
> > +static inline void prefetchw(const void *x)
> > +{
> > +       __asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory");
> > +}
> > +#endif /* CONFIG_RISCV_ISA_ZICBOP */
> >
> >  /* Do necessary setup to start up a newly executed thread. */
> >  extern void start_thread(struct pt_regs *regs,
> > --
> > 2.40.1
> >
> 
> 
> -- 
> Best Regards
>  Guo Ren
>