[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <07b35821-3b95-ce9b-8a62-7eb8cb7a8ddf@quicinc.com>
Date: Thu, 4 Jan 2024 14:14:59 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: <cros-qcom-dts-watchers@...omium.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof
Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley
<conor+dt@...nel.org>,
Stephen Boyd <swboyd@...omium.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_vbadigan@...cinc.com>,
<quic_ramkri@...cinc.com>, <quic_nitegupt@...cinc.com>,
<quic_skananth@...cinc.com>, <quic_parass@...cinc.com>,
<stable@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: qcom: sc7280: Add additional MSI interrupts
Hi All,
Can you please review this.
Thanks & Regards,
Krishna Chaitanya.
On 12/18/2023 12:01 PM, Krishna chaitanya chundru wrote:
> Current MSI's mapping was incorrect. This platform supports
> 8 vectors each vector supports 32 MSI's, so total MSI's
> supported is 256.
>
> Add all the MSI groups supported for this PCIe instance in this platform.
>
> Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
> cc: stable@...r.kernel.org
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 66f1eb83cca7..e1dc41705f61 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2146,8 +2146,16 @@ pcie1: pci@...8000 {
> ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
>
> ---
> base-commit: 5bd7ef53ffe5ca580e93e74eb8c81ed191ddc4bd
> change-id: 20231218-additional_msi-6062dc812c29
>
> Best regards,
Powered by blists - more mailing lists