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Message-ID: <ZZo3XpYkzxDolK47@lizhi-Precision-Tower-5810>
Date: Sun, 7 Jan 2024 00:32:14 -0500
From: Frank Li <Frank.li@....com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: krzysztof.kozlowski@...aro.org, bhelgaas@...gle.com,
conor+dt@...nel.org, devicetree@...r.kernel.org, festevam@...il.com,
helgaas@...nel.org, hongxing.zhu@....com, imx@...ts.linux.dev,
kernel@...gutronix.de, krzysztof.kozlowski+dt@...aro.org,
kw@...ux.com, l.stach@...gutronix.de,
linux-arm-kernel@...ts.infradead.org, linux-imx@....com,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
lpieralisi@...nel.org, robh@...nel.org, s.hauer@...gutronix.de,
shawnguo@...nel.org
Subject: Re: [PATCH v7 07/16] PCI: imx6: Simplify configure_type() by using
mode_off and mode_mask
On Sun, Jan 07, 2024 at 10:46:55AM +0530, Manivannan Sadhasivam wrote:
> On Wed, Dec 27, 2023 at 01:27:18PM -0500, Frank Li wrote:
> > Add drvdata::mode_off and drvdata::mode_mask to simple
>
> simplify
>
> > imx6_pcie_configure_type() logic.
> >
> > Signed-off-by: Frank Li <Frank.Li@....com>
>
> Couple of comments below.
>
> > ---
> >
> > Notes:
> > Change from v2 to v3
> > - none
> > Change from v1 to v2
> > - use ffs() to fixe build error.
> >
> > drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++---------
> > 1 file changed, 40 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 588bfb616260e..717e8fa030deb 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -68,6 +68,7 @@ enum imx6_pcie_variants {
> >
> > #define IMX6_PCIE_MAX_CLKS 6
> >
> > +#define IMX6_PCIE_MAX_INSTANCES 2
> > struct imx6_pcie_drvdata {
> > enum imx6_pcie_variants variant;
> > enum dw_pcie_device_mode mode;
> > @@ -77,6 +78,8 @@ struct imx6_pcie_drvdata {
> > const char *clk_names[IMX6_PCIE_MAX_CLKS];
> > const u32 ltssm_off;
> > const u32 ltssm_mask;
> > + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
> > + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
> > };
> >
> > struct imx6_pcie {
> > @@ -174,32 +177,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
> >
> > static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> > {
> > - unsigned int mask, val, mode;
> > + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> > + unsigned int mask, val, mode, id;
> >
> > - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
> > + if (drvdata->mode == DW_PCIE_EP_TYPE)
> > mode = PCI_EXP_TYPE_ENDPOINT;
> > else
> > mode = PCI_EXP_TYPE_ROOT_PORT;
> >
> > - switch (imx6_pcie->drvdata->variant) {
> > - case IMX8MQ:
> > - case IMX8MQ_EP:
> > - if (imx6_pcie->controller_id == 1) {
> > - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
> > - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > - mode);
> > - } else {
> > - mask = IMX6Q_GPR12_DEVICE_TYPE;
> > - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
> > - }
> > - break;
> > - default:
> > - mask = IMX6Q_GPR12_DEVICE_TYPE;
> > - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
> > - break;
> > - }
> > + id = imx6_pcie->controller_id;
> > +
> > + /* If mode_mask[id] is zero, means each controller have its individual gpr */
> > + if (!drvdata->mode_mask[id])
> > + id = 0;
> > +
> > + mask = drvdata->mode_mask[id];
> > + /* FIELD_PREP mask have been constant */
>
> No need of this comment.
>
> > + val = mode << (ffs(mask) - 1);
> >
> > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
> > }
> >
> > static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
> > @@ -1376,6 +1372,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy"},
> > .ltssm_off = IOMUXC_GPR12,
> > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX6SX] = {
> > .variant = IMX6SX,
> > @@ -1386,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"},
> > .ltssm_off = IOMUXC_GPR12,
> > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX6QP] = {
> > .variant = IMX6QP,
> > @@ -1397,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy"},
> > .ltssm_off = IOMUXC_GPR12,
> > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX7D] = {
> > .variant = IMX7D,
> > @@ -1405,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > IMX6_PCIE_FLAG_HAS_PHY_RESET,
> > .gpr = "fsl,imx7d-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX8MQ] = {
> > .variant = IMX8MQ,
> > @@ -1412,6 +1416,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > IMX6_PCIE_FLAG_HAS_PHY_RESET,
> > .gpr = "fsl,imx8mq-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > + .mode_off[1] = IOMUXC_GPR12,
> > + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
>
> Is the mode_mask differ between SoCs or fixed based on instances? I mean, if
> there is a guarantee that it is going to be IMX6Q_GPR12_DEVICE_TYPE for instance
> 1 and IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE for instance 2 etc...
>
> Then we can avoid these SoC specific config and simplify the code further.
No, iMX95 will change it.
Frank
>
> - Mani
>
> > },
> > [IMX8MM] = {
> > .variant = IMX8MM,
> > @@ -1420,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > IMX6_PCIE_FLAG_HAS_APP_RESET,
> > .gpr = "fsl,imx8mm-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX8MP] = {
> > .variant = IMX8MP,
> > @@ -1428,6 +1438,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > IMX6_PCIE_FLAG_HAS_APP_RESET,
> > .gpr = "fsl,imx8mp-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX8MQ_EP] = {
> > .variant = IMX8MQ_EP,
> > @@ -1436,6 +1448,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .mode = DW_PCIE_EP_TYPE,
> > .gpr = "fsl,imx8mq-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > + .mode_off[1] = IOMUXC_GPR12,
> > + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > },
> > [IMX8MM_EP] = {
> > .variant = IMX8MM_EP,
> > @@ -1443,6 +1459,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .mode = DW_PCIE_EP_TYPE,
> > .gpr = "fsl,imx8mm-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > [IMX8MP_EP] = {
> > .variant = IMX8MP_EP,
> > @@ -1450,6 +1468,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .mode = DW_PCIE_EP_TYPE,
> > .gpr = "fsl,imx8mp-iomuxc-gpr",
> > .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> > + .mode_off[0] = IOMUXC_GPR12,
> > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > },
> > };
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
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