lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZZuojgPfXZ5Bq6Kl@yilunxu-OptiPlex-7050>
Date: Mon, 8 Jan 2024 15:47:26 +0800
From: Xu Yilun <yilun.xu@...ux.intel.com>
To: Michal Simek <michal.simek@....com>
Cc: linux-kernel@...r.kernel.org, monstr@...str.eu, michal.simek@...inx.com,
	git@...inx.com, Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Moritz Fischer <mdf@...nel.org>, Rob Herring <robh+dt@...nel.org>,
	Tom Rix <trix@...hat.com>, Wu Hao <hao.wu@...el.com>,
	Xu Yilun <yilun.xu@...el.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
	kishore Manne <nava.kishore.manne@....com>,
	"open list:FPGA MANAGER FRAMEWORK" <linux-fpga@...r.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

On Fri, Jan 05, 2024 at 05:04:30PM +0100, Michal Simek wrote:
> Convert the generic fpga bridge DT binding to json-schema.
> 
> Signed-off-by: Michal Simek <michal.simek@....com>

Reviewed-by: Xu Yilun <yilun.xu@...el.com>

Thanks

> ---
> 
>  .../devicetree/bindings/fpga/fpga-bridge.txt  | 13 --------
>  .../devicetree/bindings/fpga/fpga-bridge.yaml | 30 +++++++++++++++++++
>  .../bindings/fpga/xlnx,pr-decoupler.yaml      |  5 +++-
>  3 files changed, 34 insertions(+), 14 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.txt
>  create mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
> deleted file mode 100644
> index 72e06917288a..000000000000
> --- a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -FPGA Bridge Device Tree Binding
> -
> -Optional properties:
> -- bridge-enable		: 0 if driver should disable bridge at startup
> -			  1 if driver should enable bridge at startup
> -			  Default is to leave bridge in current state.
> -
> -Example:
> -	fpga_bridge3: fpga-bridge@...25080 {
> -		compatible = "altr,socfpga-fpga2sdram-bridge";
> -		reg = <0xffc25080 0x4>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> new file mode 100644
> index 000000000000..248639c6b560
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: FPGA Bridge
> +
> +maintainers:
> +  - Michal Simek <michal.simek@....com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^fpga-bridge(@.*)?$"
> +
> +  bridge-enable:
> +    description: |
> +      0 if driver should disable bridge at startup
> +      1 if driver should enable bridge at startup
> +      Default is to leave bridge in current state.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 0, 1 ]
> +
> +additionalProperties: true
> +
> +examples:
> +  - |
> +    fpga-bridge {
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> index a7d4b8e59e19..5bf731f9d99a 100644
> --- a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> @@ -9,6 +9,9 @@ title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
>  maintainers:
>    - Nava kishore Manne <nava.kishore.manne@....com>
>  
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
>  description: |
>    The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
>    decouplers/fpga bridges. The controller can decouple/disable the bridges
> @@ -51,7 +54,7 @@ required:
>    - clocks
>    - clock-names
>  
> -additionalProperties: false
> +unevaluatedProperties: false
>  
>  examples:
>    - |
> -- 
> 2.36.1
> 
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ