linux-kernel - [PATCH V2 3/3] arm64: dts: mediatek: mt7988: add clock controllers

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Message-Id: <20240108085228.4727-4-zajec5@gmail.com>
Date: Mon,  8 Jan 2024 09:52:28 +0100
From: Rafał Miłecki <zajec5@...il.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>
Cc: Daniel Golle <daniel@...rotopia.org>,
	Hsin-Yi Wang <hsinyi@...omium.org>,
	Nícolas F . R . A . Prado <nfraprado@...labora.com>,
	jason-ch chen <Jason-ch.Chen@...iatek.com>,
	Macpaul Lin <macpaul.lin@...iatek.com>,
	Bernhard Rosenkränzer <bero@...libre.com>,
	Sean Wang <sean.wang@...iatek.com>,
	Frank Wunderlich <frank-w@...lic-files.de>,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Rafał Miłecki <rafal@...ecki.pl>
Subject: [PATCH V2 3/3] arm64: dts: mediatek: mt7988: add clock controllers

From: Rafał Miłecki <rafal@...ecki.pl>

Add bindings of on-SoC clocks.

Signed-off-by: Rafał Miłecki <rafal@...ecki.pl>
---
V2: New PATCH in the series thanks to Daniel's bindings work

 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 41 ++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 5a778188ac21..bba97de4fb44 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -78,12 +78,51 @@ gic: interrupt-controller@...0000 {
 			#interrupt-cells = <3>;
 		};
 
-		watchdog@...1c000 {
+		clock-controller@...01000 {
+			compatible = "mediatek,mt7988-infracfg", "syscon";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		clock-controller@...1b000 {
+			compatible = "mediatek,mt7988-topckgen", "syscon";
+			reg = <0 0x1001b000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		watchdog: watchdog@...1c000 {
 			compatible = "mediatek,mt7988-wdt";
 			reg = <0 0x1001c000 0 0x1000>;
 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			#reset-cells = <1>;
 		};
+
+		clock-controller@...1e000 {
+			compatible = "mediatek,mt7988-apmixedsys";
+			reg = <0 0x1001e000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		clock-controller@...40000 {
+			compatible = "mediatek,mt7988-xfi-pll";
+			reg = <0 0x11f40000 0 0x1000>;
+			resets = <&watchdog 16>;
+			#clock-cells = <1>;
+		};
+
+		clock-controller@...00000 {
+			compatible = "mediatek,mt7988-ethsys", "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		clock-controller@...31000 {
+			compatible = "mediatek,mt7988-ethwarp";
+			reg = <0 0x15031000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
 	};
 
 	timer {
-- 
2.35.3