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Message-ID: <ZZvLCmUqAriMV/Va@gmail.com>
Date: Mon, 8 Jan 2024 11:14:34 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org,
x86@...nel.org
Subject: [GIT PULL] IRQ subsystem changes for v6.8
Linus,
Please pull the latest irq/core git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-core-2024-01-08
# HEAD: 69ffab9b9e698248cbb4042e47f82afb00dc1bb4 irqchip/irq-xtensa-pic: Clean up
IRQ subsystem changes for v6.8:
Drivers:
- Add support for the IA55 interrupt controller on RZ/G3S SoC's
- Update/fix the Qualcom MPM Interrupt Controller driver's
register enumeration within the somewhat exotic "RPM Message RAM"
MMIO-mapped shared memory region that is used for other purposes
as well.
- Clean up the Xtensa built-in Programmable Interrupt Controller
driver (xtensa-pic) a bit.
Thanks,
Ingo
------------------>
Claudiu Beznea (7):
irqchip/renesas-rzg2l: Use tabs instead of spaces
irqchip/renesas-rzg2l: Align struct member names to tabs
irqchip/renesas-rzg2l: Document structure members
irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
irqchip/renesas-rzg2l: Add support for suspend to RAM
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
Konrad Dybcio (2):
dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle
irqchip/qcom-mpm: Support passing a slice of SRAM as reg space
Max Filippov (1):
irqchip/irq-xtensa-pic: Clean up
.../bindings/interrupt-controller/qcom,mpm.yaml | 52 ++++++----
.../interrupt-controller/renesas,rzg2l-irqc.yaml | 5 +-
drivers/irqchip/irq-qcom-mpm.c | 26 ++++-
drivers/irqchip/irq-renesas-rzg2l.c | 110 ++++++++++++++++-----
drivers/irqchip/irq-xtensa-pic.c | 31 +++---
5 files changed, 157 insertions(+), 67 deletions(-)
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