linux-kernel - [PATCH] arm64: mm: disable PAN during caches_clean_inval_user

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Message-ID: <e6dc8a44a140d1e54bc1408c36704b581433ec10.camel@lenze.com>
Date: Mon, 8 Jan 2024 13:00:39 +0000
From: "Brandt, Oliver - Lenze" <oliver.brandt@...ze.com>
To: "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "will@...nel.org" <will@...nel.org>,
	"catalin.marinas@....com" <catalin.marinas@....com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: [PATCH] arm64: mm: disable PAN during caches_clean_inval_user_pou

Using the cacheflush() syscall from an 32-bit user-space fails when
ARM64_PAN is used. We 'll get an endless loop:

	1. executing "dc cvau, x2" results in raising an abort
	2. abort handler does not fix the reason for the abort and
	   returns to 1.

Disabling PAN for the time of the cache maintenance fixes this.

Fixes: 338d4f49d6f7 ("arm64: kernel: Add support for Privileged Access Never")
Cc: stable@...r.kernel.org
Signed-off-by: Oliver Brandt <oliver.brandt@...ze.com>
---
 arch/arm64/mm/cache.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 503567c864fde..333c4c2baa568 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -70,10 +70,12 @@ SYM_FUNC_ALIAS(__pi_caches_clean_inval_pou, caches_clean_inval_pou)
  */
 SYM_FUNC_START(caches_clean_inval_user_pou)
 	uaccess_ttbr0_enable x2, x3, x4
+	ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
 
 	caches_clean_inval_pou_macro 2f
 	mov	x0, xzr
 1:
+	ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
 	uaccess_ttbr0_disable x1, x2
 	ret
 2:
-- 
2.43.0