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Message-ID: <ZZwgbz4J_R8E1_uQ@google.com>
Date: Mon, 8 Jan 2024 08:18:55 -0800
From: Sean Christopherson <seanjc@...gle.com>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCHv2] x86/trampoline: Bypass compat mode in
trampoline_start64() if not needed
On Sun, Jan 07, 2024, Kirill A. Shutemov wrote:
> @@ -220,6 +222,33 @@ SYM_CODE_START(trampoline_start64)
> lidt tr_idt(%rip)
> lgdt tr_gdt64(%rip)
>
> + /* Check if paging mode has to be changed */
> + movq %cr4, %rax
> + xorq tr_cr4(%rip), %rax
This is buggy, tr_cr4 is only 4 bytes. And even if tr_cr4 were 8 bytes, the reason
why nothing showed up in testing is also why only 4 bytes need to be XOR'd: the
upper 32 bits of the result are never consumed.
> + andq $X86_CR4_LA57, %rax
Nit, this can be TEST instead of AND, e.g. I was looking to see if RAX was used
anywhere in the flow. And in theory it's possible a CPU could support uop fusing
for TEST+Jcc but not AND+Jcc, cause shaving a cycle in this code is obviously
super important ;-)
And as above, testl, not testq.
> + jnz .L_switch_paging
> +
> + /* Paging mode is correct proceed in 64-bit mode */
> +
> + LOCK_AND_LOAD_REALMODE_ESP lock_rip=1
> +
> + movw $__KERNEL_DS, %dx
> + movl %edx, %ss
> + addl $pa_real_mode_base, %esp
> + movl %edx, %ds
> + movl %edx, %es
> + movl %edx, %fs
> + movl %edx, %gs
> +
> + movl $pa_trampoline_pgd, %eax
> + movq %rax, %cr3
> +
> + jmpq *tr_start(%rip)
> +.L_switch_paging:
> + /*
> + * To switch between 4- and 5-level paging modes, it is necessary
> + * to disable paging. This must be done in the compatibility mode.
> + */
> ljmpl *tr_compat(%rip)
> SYM_CODE_END(trampoline_start64)
>
> --
> 2.41.0
>
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