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Message-ID: <20240108135421.684263-3-tmaimon77@gmail.com>
Date: Mon, 8 Jan 2024 15:54:15 +0200
From: Tomer Maimon <tmaimon77@...il.com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <tali.perry1@...il.com>,
<joel@....id.au>, <venture@...gle.com>, <yuenn@...gle.com>,
<benjaminfair@...gle.com>
CC: <openbmc@...ts.ozlabs.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, Tomer Maimon
<tmaimon77@...il.com>
Subject: [PATCH v22 2/8] arm64: dts: nuvoton: npcm8xx: add refernace clock
Add 25Mhz reference clock since the reference clock in not a part of
Nuvoton BMC NPCM8XX SoC.
Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
---
.../arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 10 ++++++----
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 ++++++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index ecd171b2feba..9c4df91031e7 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -58,6 +58,8 @@ clk: clock-controller@...01000 {
compatible = "nuvoton,npcm845-clk";
#clock-cells = <1>;
reg = <0x0 0xf0801000 0x0 0x1000>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
};
apb {
@@ -81,7 +83,7 @@ timer0: timer@...0 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
clock-names = "refclk";
};
@@ -153,7 +155,7 @@ watchdog0: watchdog@...c {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x801c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -162,7 +164,7 @@ watchdog1: watchdog@...c {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x901c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -171,7 +173,7 @@ watchdog2: watchdog@...c {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xa01c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
};
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
index a5ab2bc0f835..722a46d78d23 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -19,6 +19,12 @@ chosen {
memory {
reg = <0x0 0x0 0x0 0x40000000>;
};
+
+ refclk: refclk-25mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
};
&serial0 {
--
2.34.1
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