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Message-Id: <20240109071246.24065-2-shengyang.chen@starfivetech.com>
Date: Tue, 9 Jan 2024 15:12:45 +0800
From: Shengyang Chen <shengyang.chen@...rfivetech.com>
To: devicetree@...r.kernel.org,
linux-phy@...ts.infradead.org
Cc: vkoul@...nel.org,
kishon@...nel.org,
robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
p.zabel@...gutronix.de,
minda.chen@...rfivetech.com,
changhuang.liang@...rfivetech.com,
rogerq@...nel.org,
geert+renesas@...der.be,
keith.zhao@...rfivetech.com,
shengyang.chen@...rfivetech.com,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/2] dt-bindings: phy: Add starfive,jh7110-dphy-tx
StarFive SoCs like the jh7110 use a MIPI D-PHY TX
controller based on a M31 IP. Add a binding for it.
Signed-off-by: Shengyang Chen <shengyang.chen@...rfivetech.com>
---
.../bindings/phy/starfive,jh7110-dphy-tx.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
new file mode 100644
index 000000000000..4a06a2642b4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SoC MIPI D-PHY Tx Controller
+
+maintainers:
+ - Keith Zhao <keith.zhao@...rfivetech.com>
+ - Shengyang Chen <shengyang.chen@...rfivetech.com>
+
+description:
+ The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
+ DSI data.
+
+properties:
+ compatible:
+ const: starfive,jh7110-dphy-tx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: txesc
+
+ resets:
+ items:
+ - description: MIPITX_DPHY_SYS reset
+
+ reset-names:
+ items:
+ - const: sys
+
+ power-domains:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@...e0000 {
+ compatible = "starfive,jh7110-dphy-tx";
+ reg = <0x295e0000 0x10000>;
+ clocks = <&voutcrg 14>;
+ clock-names = "txesc";
+ resets = <&syscrg 10>;
+ reset-names = "sys";
+ power-domains = <&aon_syscon 0>;
+ #phy-cells = <0>;
+ };
--
2.17.1
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