| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 9 Jan 2024 17:23:26 +0900
From: Yoshinori Sato <ysato@...rs.sourceforge.jp>
To: linux-sh@...r.kernel.org
Cc: Yoshinori Sato <ysato@...rs.sourceforge.jp>,
Damien Le Moal <dlemoal@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Thomas Gleixner <tglx@...utronix.de>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Rich Felker <dalias@...c.org>,
John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
Lee Jones <lee@...nel.org>,
Helge Deller <deller@....de>,
Heiko Stuebner <heiko@...ech.de>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Chris Morgan <macromorgan@...mail.com>,
Yang Xiwen <forbidden405@...mail.com>,
Sebastian Reichel <sre@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Randy Dunlap <rdunlap@...radead.org>,
Arnd Bergmann <arnd@...db.de>,
Vlastimil Babka <vbabka@...e.cz>,
Hyeonggon Yoo <42.hyeyoo@...il.com>,
David Rientjes <rientjes@...gle.com>,
Baoquan He <bhe@...hat.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Guenter Roeck <linux@...ck-us.net>,
Stephen Rothwell <sfr@...b.auug.org.au>,
Azeem Shaikh <azeemshaikh38@...il.com>,
Javier Martinez Canillas <javierm@...hat.com>,
Max Filippov <jcmvbkbc@...il.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Bin Meng <bmeng@...ylab.org>,
Jonathan Corbet <corbet@....net>,
Jacky Huang <ychuang3@...oton.com>,
Lukas Bulwahn <lukas.bulwahn@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
Sam Ravnborg <sam@...nborg.org>,
Sergey Shtylyov <s.shtylyov@....ru>,
Michael Karcher <kernel@...rcher.dialup.fu-berlin.de>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
linux-ide@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-pci@...r.kernel.org,
linux-serial@...r.kernel.org,
linux-fbdev@...r.kernel.org
Subject: [DO NOT MERGE v6 29/37] sh: SH7751R SoC Internal peripheral definition dtsi.
SH7751R internal peripherals device tree.
Signed-off-by: Yoshinori Sato <ysato@...rs.sourceforge.jp>
---
arch/sh/boot/dts/sh7751r.dtsi | 148 ++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index 000000000000..f006f7bacf99
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include <dt-bindings/interrupt-controller/renesas,sh7751-intc.h>
+#include <dt-bindings/clock/sh7750-cpg.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh2";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&cpg SH7750_CPG_ICK>;
+ clock-names = "ick";
+ icache-size = <16384>;
+ icache-line-size = <32>;
+ dcache-size = <32768>;
+ dcache-line-size = <32>;
+ };
+ };
+
+ xtal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xtal";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&shintc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cpg: clock-controller@...00000 {
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ compatible = "renesas,sh7751r-cpg";
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ reg = <0xffc00000 20>, <0xfe0a0000 16>;
+ reg-names = "FRQCR", "CLKSTP00";
+ renesas,mode = <0>;
+ };
+
+ shintc: interrupt-controller@...00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd00000 20>, <0xfe080000 128>;
+ reg-names = "ICR", "INTPRI00";
+ renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */
+ <0x2a0 IPRD IPR_B8>, /* IRL1 */
+ <0x300 IPRD IPR_B4>, /* IRL2 */
+ <0x360 IPRD IPR_B0>, /* IRL3 */
+ <0x400 IPRA IPR_B12>, /* TMU0 */
+ <0x420 IPRA IPR_B8>, /* TMU1 */
+ <0x440 IPRA IPR_B4>, /* TMU2 TNUI */
+ <0x460 IPRA IPR_B4>, /* TMU2 TICPI */
+ <0x480 IPRA IPR_B0>, /* RTC ATI */
+ <0x4a0 IPRA IPR_B0>, /* RTC PRI */
+ <0x4c0 IPRA IPR_B0>, /* RTC CUI */
+ <0x4e0 IPRB IPR_B4>, /* SCI ERI */
+ <0x500 IPRB IPR_B4>, /* SCI RXI */
+ <0x520 IPRB IPR_B4>, /* SCI TXI */
+ <0x540 IPRB IPR_B4>, /* SCI TEI */
+ <0x560 IPRB IPR_B12>, /* WDT */
+ <0x580 IPRB IPR_B8>, /* REF RCMI */
+ <0x5a0 IPRB IPR_B4>, /* REF ROVI */
+ <0x600 IPRC IPR_B0>, /* H-UDI */
+ <0x620 IPRC IPR_B12>, /* GPIO */
+ <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */
+ <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */
+ <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */
+ <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */
+ <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */
+ <0x700 IPRC IPR_B4>, /* SCIF ERI */
+ <0x720 IPRC IPR_B4>, /* SCIF RXI */
+ <0x740 IPRC IPR_B4>, /* SCIF BRI */
+ <0x760 IPRC IPR_B4>, /* SCIF TXI */
+ <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */
+ <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */
+ <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */
+ <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */
+ <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */
+ <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */
+ <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */
+ <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */
+ <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */
+ <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */
+ <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */
+ <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */
+ <0xb00 INTPRI00 IPR_B8>, /* TMU3 */
+ <0xb80 INTPRI00 IPR_B12>; /* TMU4 */
+ };
+
+ /* sci0 is rarely used, so it is not defined here. */
+ scif1: serial@...80000 {
+ compatible = "renesas,scif-sh7751", "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <0x700>,
+ <0x720>,
+ <0x760>,
+ <0x740>;
+ interrupt-names = "eri", "rxi", "txi", "bri";
+ clocks = <&cpg SH7750_MSTP_SCIF>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
+ tmu0: timer@...80000 {
+ compatible = "renesas,tmu-sh7750", "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <0x400>,
+ <0x420>,
+ <0x440>,
+ <0x460>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+ clocks = <&cpg SH7750_MSTP_TMU012>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ #renesas,channels = <3>;
+ };
+
+ pcic: pci@...00000 {
+ compatible = "renesas,sh7751-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ bus-range = <0 0>;
+ reg = <0xfe200000 0x0400>,
+ <0xff800000 0x0100>;
+ status = "disabled";
+ };
+ };
+};
--
2.39.2
Powered by blists - more mailing lists