linux-kernel - Re: [RFC PATCH 3/6] iommu/amd: Introduce Guest-ID struct amd_iommu

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Message-ID: <fc15b460-9e1a-4e68-ad5d-ab1c871c1300@amd.com>
Date: Tue, 9 Jan 2024 16:52:05 +0700
From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@....com>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: "Tian, Kevin" <kevin.tian@...el.com>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
 "joro@...tes.org" <joro@...tes.org>, "Liu, Yi L" <yi.l.liu@...el.com>,
 "nicolinc@...dia.com" <nicolinc@...dia.com>,
 "eric.auger@...hat.com" <eric.auger@...hat.com>,
 "vasant.hegde@....com" <vasant.hegde@....com>,
 "jon.grimm@....com" <jon.grimm@....com>,
 "santosh.shukla@....com" <santosh.shukla@....com>,
 "Dhaval.Giani@....com" <Dhaval.Giani@....com>,
 "pandoh@...gle.com" <pandoh@...gle.com>,
 "loganodell@...gle.com" <loganodell@...gle.com>
Subject: Re: [RFC PATCH 3/6] iommu/amd: Introduce Guest-ID struct
 amd_iommu_vminfo



On 1/5/2024 9:38 PM, Jason Gunthorpe wrote:
> On Fri, Jan 05, 2024 at 08:39:56PM +0700, Suthikulpanit, Suravee wrote:
>> Hi Kevin
>>
>> On 12/15/2023 2:35 PM, Tian, Kevin wrote:
>>>> From: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
>>>> Sent: Wednesday, December 13, 2023 12:02 AM
>>>>
>>>> AMD HW-vIOMMU feature requires IOMMU driver to specify a unique 16-bit
>>>> Guest ID (GID) for each VM. This ID is used to index into various
>>>> data structures for configuring the hardware.
>>>>
>>>> Introduce amd_iommu_vminfo_hash hashtable to store per-vm
>>>> configuration,
>>>> which uses 16-bit GID as a hash key along with helper functions.
>>>>
>>>
>>> somehow it's unclear to me whether this series is only for hw
>>> supporting vf or broader hw supporting nested capability. for
>>> the latter case is GID still necessary?
>>
>> I am restructuring the series and might be moving GID stuff until later when
>> introduce broader hw support for AMD vIOMMU.
> 
> I'm hoping you can just skip enabling the viommu features and still
> have nesting? That should be OK right? The SW will manage the
> invalidations.

Correct, the part 1 only add support for nested translation (w/o 
HW-vIOMMU feature). So, SW would need to manage the invalidation.

Suravee