linux-kernel - Re: [PATCH v4 0/5] support ipq5332 platform

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Message-ID: <eedcf2b7-66e9-45be-8ef2-ae6f875bdb5f@quicinc.com>
Date: Tue, 9 Jan 2024 19:35:30 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>,
        Andrew Lunn
	<andrew@...n.ch>
CC: Sergey Ryazanov <ryazanov.s.a@...il.com>, <agross@...nel.org>,
        <andersson@...nel.org>, <konrad.dybcio@...aro.org>,
        <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <hkallweit1@...il.com>, <robert.marko@...tura.hr>,
        <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_srichara@...cinc.com>
Subject: Re: [PATCH v4 0/5] support ipq5332 platform



On 1/8/2024 11:53 PM, Russell King (Oracle) wrote:
> On Sat, Jan 06, 2024 at 04:45:08PM +0100, Andrew Lunn wrote:
>>> I just realized that the UNIPHY block is a MII (probably SGMII) controller.
>>> Isn't it? And I expect that it responsible more then just for clock
>>> enabling. It should also activate and perform a basic configuration of MII
>>> for actual data transmission. If so, then it should placed somewhere under
>>> drivers/net/phy or drivers/net/pcs.
>>
>> Before we decide that, we need a description of what the UNIPHY
>> actually does, what registers it has, etc. Sometimes blocks like this
>> get split into a generic PHY, aka drivers/phy/ and a PCS driver. This
>> would be true if the UNIPHY is also used for USB SERDES, SATA SERDES
>> etc. The SERDES parts go into a generic PHY driver, and the SGMII on
>> to of the SERDES is placed is a PCS driver.
>>
>> The problem i have so far is that there is no usable description of
>> any of this hardware, and the developers trying to produce drivers for
>> this hardware don't actually seem to understand the Linux architecture
>> for things like this.
> 
> +1. I think it's now more convoluted than ever, and someone needs to
> take a step back, look at the hardware, look at the kernel model, and
> work out how to implement this. It needs to be explained in a clear
> and concise way in _one_ go, not spread over multiple emails. Probably
> with ASCII art diagrams showing the structure.
> 
> If that isn't possible, then someone needs to provide a detailed
> description of the hardware so that the subsystem maintainers get a
> proper view of what this hardware is so they can advise. This is the
> least preferable option due to the maintainer time it takes.
> 
> If neither of these two things happen, then I'm afraid all bets are
> off for getting this into the kernel.
> 

Thanks Russell for suggestions.
I will provide the diagram of the hardware and the description in the
cover letter of new patch set, i know it is really important to for the
review smoothly.

Christian's work is designing the PHY package level DT, which is very
suitable for the complex clock configs of qca8084 PHY, i also provides
some descriptions of the qca8084 PHY, it will be very welcome to
review the clock DT model of qca8084 PHY.