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Message-ID: <ZZyuu2UZuz8OvZ1B@tassilo>
Date: Mon, 8 Jan 2024 18:26:03 -0800
From: Andi Kleen <ak@...ux.intel.com>
To: "Huang, Kai" <kai.huang@...el.com>
Cc: "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"hpa@...or.com" <hpa@...or.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>,
"seanjc@...gle.com" <seanjc@...gle.com>
Subject: Re: [PATCHv2] x86/trampoline: Bypass compat mode in
trampoline_start64() if not needed
> This seems depends on the BIOS will always use 4-level paging. Can we make such
> assumption?
Yes I believe it's fine. All BIOS on 5 level capable systems currently
only use 4-level when passing control to someone else.
(although I cannot find the quote in the UEFI spec currently, will check
on that)
The UEFI run time environment is defined as 4-level. Changing that would
break compatibility OS supprt at least for run time services.
>
> > +
> > + /* Paging mode is correct proceed in 64-bit mode */
> > +
> > + LOCK_AND_LOAD_REALMODE_ESP lock_rip=1
> > +
> > + movw $__KERNEL_DS, %dx
> > + movl %edx, %ss
> > + addl $pa_real_mode_base, %esp
> > + movl %edx, %ds
> > + movl %edx, %es
> > + movl %edx, %fs
> > + movl %edx, %gs
> > +
> > + movl $pa_trampoline_pgd, %eax
> > + movq %rax, %cr3
> > +
> > + jmpq *tr_start(%rip)
>
> IIUC you won't be using __KERNEL_CS in this case? Not sure whether this matters
> though, because the spec says in 64-bit mode the hardware treats CS,DS,ES,SS as
> zero.
That's a good catch. Might be better to use __KERNEL_CS. Otherwise if a
IRET happens later and it tries to reload CS it might fault. Probably
doesn't happen before another reload happens anyways, but it's better
to avoid it.
-Andi
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