linux-kernel - Re: [PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

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Message-ID: <550cf801-431e-46e7-9f1d-7e80878ab40a@quicinc.com>
Date: Wed, 10 Jan 2024 16:47:48 +0530
From: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>, <will@...nel.org>,
        <robin.murphy@....com>, <joro@...tes.org>,
        <dmitry.baryshkov@...aro.org>, <jsnitsel@...hat.com>,
        <quic_bjorande@...cinc.com>, <mani@...nel.org>,
        <quic_eberman@...cinc.com>, <robdclark@...omium.org>,
        <u.kleine-koenig@...gutronix.de>, <robh@...nel.org>,
        <vladimir.oltean@....com>, <quic_pkondeti@...cinc.com>,
        <quic_molvera@...cinc.com>
CC: <linux-arm-msm@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <iommu@...ts.linux.dev>, <linux-kernel@...r.kernel.org>,
        <qipl.kernel.upstream@...cinc.com>
Subject: Re: [PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu
 reset operation



On 1/10/2024 4:30 PM, Konrad Dybcio wrote:
> 
> 
> On 1/9/24 12:42, Bibek Kumar Patro wrote:
>> Default MMU-500 reset operation disables context caching in
>> prefetch buffer. It is however expected for context banks using
>> the ACTLR register to retain their prefetch value during reset
>> and runtime suspend.
>>
>> Replace default MMU-500 reset operation with Qualcomm specific reset
>> operation which envelope the default reset operation and re-enables
>> context caching in prefetch buffer for Qualcomm SoCs.
>>
>> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
>> ---
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++--
>>   1 file changed, 34 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c 
>> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 549ae4dba3a6..000e207346af 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> @@ -14,6 +14,16 @@
>>
>>   #define QCOM_DUMMY_VAL    -1
>>
>> +/*
>> + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
>> + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
>> + * buffer). The remaining bits are implementation defined and vary 
>> across
>> + * SoCs.
>> + */
>> +
>> +#define CPRE            (1 << 1)
>> +#define CMTLB            (1 << 0)
>> +
>>   static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
>>   {
>>       return container_of(smmu, struct qcom_smmu, smmu);
>> @@ -376,11 +386,32 @@ static int qcom_smmu_def_domain_type(struct 
>> device *dev)
>>       return match ? IOMMU_DOMAIN_IDENTITY : 0;
>>   }
>>
>> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
>> +{
>> +    int ret;
>> +    u32 val;
>> +    int i;
>> +
>> +    ret = arm_mmu500_reset(smmu);
>> +
>> +    if (ret)
> Weird empty line.. Please remove it in the next revision since you're
> already going to send a new one..
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> 

Ack, thanks for pointing this out.
Will remove this while sending out the new patch.

Thanks & regards,
Bibek

> Konrad