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Message-ID: <CABgObfaByKFKRtLpY1yAJFmcY1WxWcn3tpeVw7Nho+qk0PFUbQ@mail.gmail.com>
Date: Thu, 11 Jan 2024 21:02:18 +0100
From: Paolo Bonzini <pbonzini@...hat.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Tao Su <tao1.su@...ux.intel.com>, Chao Gao <chao.gao@...el.com>,
Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org, Yi Lai <yi1.lai@...el.com>,
Xudong Hao <xudong.hao@...el.com>
Subject: Re: [PATCH] x86/cpu: Add a VMX flag to enumerate 5-level EPT support
to userspace
On Thu, Jan 11, 2024 at 5:25 PM Sean Christopherson <seanjc@...gle.com> wrote:
> > It is unusual to assign a huge RAM to guest, but passthrough a device also may trigger
> > this issue which we have met, i.e. alloc memslot for the 64bit BAR which can set
> > bits[51:48]. BIOS can control the BAR address, e.g. seabios moved 64bit pci window
> > to end of address space by using advertised physical bits[1].
>
> Drat. Do you know if these CPUs are going to be productized? We'll still need
> something in KVM either way, but whether or not the problems are more or less
> limited to funky software setups might influence how we address this.
Wait, we do have an API for guest physical address size. It's
KVM_GET_SUPPORTED_CPUID2: the # of bits is in leaf 0x80000008, bits
0:7 of EAX. In fact that leaf is what firmware uses to place the BARs.
So it just needs to be adjusted for VMX in __do_cpuid_func, and looked
up in selftests.
Paolo
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