linux-kernel - [PATCH v11 7/8] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation

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Message-Id: <20240111041015.47920-8-yi.l.liu@intel.com>
Date: Wed, 10 Jan 2024 20:10:14 -0800
From: Yi Liu <yi.l.liu@...el.com>
To: joro@...tes.org,
	alex.williamson@...hat.com,
	jgg@...dia.com,
	kevin.tian@...el.com,
	robin.murphy@....com,
	baolu.lu@...ux.intel.com
Cc: cohuck@...hat.com,
	eric.auger@...hat.com,
	nicolinc@...dia.com,
	kvm@...r.kernel.org,
	mjrosato@...ux.ibm.com,
	chao.p.peng@...ux.intel.com,
	yi.l.liu@...el.com,
	yi.y.sun@...ux.intel.com,
	peterx@...hat.com,
	jasowang@...hat.com,
	shameerali.kolothum.thodi@...wei.com,
	lulu@...hat.com,
	suravee.suthikulpanit@....com,
	iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	linux-kselftest@...r.kernel.org,
	zhenzhong.duan@...el.com,
	joao.m.martins@...cle.com,
	xin.zeng@...el.com,
	yan.y.zhao@...el.com,
	j.granados@...sung.com,
	binbin.wu@...ux.intel.com
Subject: [PATCH v11 7/8] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation

This adds the data structure invalidating caches for the nested domain
allocated with IOMMU_HWPT_DATA_VTD_S1 type.

Reviewed-by: Kevin Tian <kevin.tian@...el.com>
Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>
Signed-off-by: Yi Liu <yi.l.liu@...el.com>
---
 include/uapi/linux/iommufd.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
index 824560c50ec6..1dfeaa2e649e 100644
--- a/include/uapi/linux/iommufd.h
+++ b/include/uapi/linux/iommufd.h
@@ -623,6 +623,42 @@ enum iommu_hwpt_invalidate_data_type {
 	IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
 };
 
+/**
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
+ *                                           stage-1 cache invalidation
+ * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
+ *                            to all-levels page structure cache or just
+ *                            the leaf PTE cache.
+ */
+enum iommu_hwpt_vtd_s1_invalidate_flags {
+	IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
+ *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
+ * @addr: The start address of the range to be invalidated. It needs to
+ *        be 4KB aligned.
+ * @npages: Number of contiguous 4K pages to be invalidated.
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
+ * @__reserved: Must be 0
+ *
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
+ * invalidation in nested translation. Userspace uses this structure to
+ * tell the impacted cache scope after modifying the stage-1 page table.
+ *
+ * Invalidating all the caches related to the page table by setting @addr
+ * to be 0 and @npages to be U64_MAX.
+ *
+ * The device TLB will be invalidated automatically if ATS is enabled.
+ */
+struct iommu_hwpt_vtd_s1_invalidate {
+	__aligned_u64 addr;
+	__aligned_u64 npages;
+	__u32 flags;
+	__u32 __reserved;
+};
+
 /**
  * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
  * @size: sizeof(struct iommu_hwpt_invalidate)
-- 
2.34.1