linux-kernel - Re: [PATCH 02/18] tty: serial: samsung: set UPIO

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAPLW+4kgfvp93O9ehZrnA5qTd7YO0Ln+S06OCiGVk=kNNf8rHA@mail.gmail.com>
Date: Tue, 16 Jan 2024 12:12:44 -0600
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: krzysztof.kozlowski@...aro.org, alim.akhtar@...sung.com, 
	gregkh@...uxfoundation.org, jirislaby@...nel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org, 
	andre.draszik@...aro.org, peter.griffin@...aro.org, kernel-team@...roid.com, 
	willmcvicker@...gle.com
Subject: Re: [PATCH 02/18] tty: serial: samsung: set UPIO_MEM32 iotype for gs101

On Wed, Jan 10, 2024 at 4:21 AM Tudor Ambarus <tudor.ambarus@...aroorg> wrote:
>
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible.
> Update the uart info name to be GS101 specific in order to
> differentiate from the other exynos platforms. All the other settings
> are not changed.
>
> exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data
> because the iotype restriction is gs101 specific and there was no other
> user of exynos_fifoszdt_serial_drv_data.
>
> Reviewed-by: Peter Griffin <peter.griffin@...aro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>

>  drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++---------
>  1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index b8fe9df20202..20ec6ef1a52f 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2495,25 +2495,43 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
>         .fifosize = { 256, 64, 64, 64 },
>  };
>
> -/*
> - * Common drv_data struct for platforms that specify samsung,uart-fifosize in
> - * device tree.
> - */
> -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
> -       EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> +       .info = {
> +               .name           = "Google GS101 UART",
> +               .type           = TYPE_S3C6400,
> +               .port_type      = PORT_S3C6400,
> +               .iotype         = UPIO_MEM32,
> +               .has_divslot    = 1,
> +               .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
> +               .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
> +               .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
> +               .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
> +               .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
> +               .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
> +               .def_clk_sel    = S3C2410_UCON_CLKSEL0,
> +               .num_clks       = 1,
> +               .clksel_mask    = 0,
> +               .clksel_shift   = 0,
> +       },
> +       .def_cfg = {
> +               .ucon           = S5PV210_UCON_DEFAULT,
> +               .ufcon          = S5PV210_UFCON_DEFAULT,
> +               .has_fracval    = 1,
> +       },
> +       /* samsung,uart-fifosize must be specified in the device tree. */
>         .fifosize = { 0 },
>  };
>
>  #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
>  #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
>  #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>
>  #else
>  #define EXYNOS4210_SERIAL_DRV_DATA NULL
>  #define EXYNOS5433_SERIAL_DRV_DATA NULL
>  #define EXYNOS850_SERIAL_DRV_DATA NULL
> -#define EXYNOS_FIFOSZDT_DRV_DATA NULL
> +#define GS101_SERIAL_DRV_DATA NULL
>  #endif
>
>  #ifdef CONFIG_ARCH_APPLE
> @@ -2601,7 +2619,7 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
>                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
>         }, {
>                 .name           = "gs101-uart",
> -               .driver_data    = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
> +               .driver_data    = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
>         },
>         { },
>  };
> @@ -2624,7 +2642,7 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
>         { .compatible = "axis,artpec8-uart",
>                 .data = ARTPEC8_SERIAL_DRV_DATA },
>         { .compatible = "google,gs101-uart",
> -               .data = EXYNOS_FIFOSZDT_DRV_DATA },
> +               .data = GS101_SERIAL_DRV_DATA },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
> --
> 2.43.0.472.g3155946c3a-goog
>
>