linux-kernel - Re: [PATCH v3 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration

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Message-ID: <CAPLW+4k9TTcp9p3dUOVpx2M-YGy+_V1p3Q3zdBvTcCqw9ytsDA@mail.gmail.com>
Date: Wed, 17 Jan 2024 10:12:28 -0600
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: peter.griffin@...aro.org, krzysztof.kozlowski+dt@...aro.org, 
	gregkh@...uxfoundation.org, mturquette@...libre.com, sboyd@...nel.org, 
	robh+dt@...nel.org, conor+dt@...nel.org, andi.shyti@...nel.org, 
	alim.akhtar@...sung.com, jirislaby@...nel.org, s.nawrocki@...sung.com, 
	tomasz.figa@...il.com, cw00.choi@...sung.com, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org, 
	linux-serial@...r.kernel.org, andre.draszik@...aro.org, 
	kernel-team@...roid.com, willmcvicker@...gle.com
Subject: Re: [PATCH v3 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration

On Wed, Jan 17, 2024 at 9:08 AM Tudor Ambarus <tudor.ambarus@...aroorg> wrote:
>
>
>
> On 1/16/24 18:03, Sam Protsenko wrote:
> >> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
> >> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
> >> selection of the protocol is intentionally left for the board dts file.
> >>
> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>
> >> ---
> >> v3: reorder usi8 clock order (thanks Andre'!). Did not make any
> >> difference at testing as the usi driver treats the clocks in bulk.
> >> v2:
> >> - identify and use gate clocks instead of dividers
> >> - move cells and pinctrl properties from dts to dtsi
> >> - move IRQ type constant on the previous line
> >>
> >>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
> >>  1 file changed, 29 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> index 6aa25cc4676e..f14a24628d04 100644
> >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@...40000 {
> >>                         interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
> >>                 };
> >>
> >> +               usi8: usi@...700c0 {
> >> +                       compatible = "google,gs101-usi",
> >> +                                    "samsung,exynos850-usi";
> >> +                       reg = <0x109700c0 0x20>;
> >> +                       ranges;
> >> +                       #address-cells = <1>;
> >> +                       #size-cells = <1>;
> >> +                       clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
> >> +                                <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
> >> +                       clock-names = "pclk", "ipclk";
> >> +                       samsung,sysreg = <&sysreg_peric0 0x101c>;
> > I'd also add samsung,mode for the "default" USI mode here, just to
> > avoid providing it later in the board's dts. But that's a matter of
> > taste I guess.
> >
>
> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
> selection of the protocol is intentionally left for the board dts file.
>
> I wanted to emphasize that USI8 doesn't have any HW defaults and its
> mode must be chosen by each particular board.
>
> I mentioned the same in the commit message, please tell if you feel it
> needs updating.
>

No, thanks, everything LGTM, I already added my R-b tag above.

> Cheers,
> ta