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Message-ID: <3f9f779c-a32f-4925-9ff9-a706861d3357@moroto.mountain>
Date: Wed, 17 Jan 2024 21:32:08 +0300
From: Dan Carpenter <dan.carpenter@...aro.org>
To: Niklas Cassel <niklas.cassel@....com>
Cc: Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
kernel-janitors@...r.kernel.org
Subject: [PATCH] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
The "msg_addr" variable is u64. However, the "tbl_offset" is an unsigned
int. This means that when the code does
msg_addr &= ~aligned_offset;
it will unintentionally zero out the high 32 bits. Declare "tbl_offset"
as a u64 to address this bug.
Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
---
>From static analysis (not tested).
drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b..2b6607c23541 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -525,7 +525,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie_ep_func *ep_func;
struct pci_epc *epc = ep->epc;
u32 reg, msg_data, vec_ctrl;
- unsigned int aligned_offset;
+ u64 aligned_offset;
u32 tbl_offset;
u64 msg_addr;
int ret;
--
2.43.0
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