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Message-ID: <20240119082233.GF2866@thinkpad>
Date: Fri, 19 Jan 2024 13:52:33 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Frank Li <Frank.Li@....com>
Cc: krzysztof.kozlowski@...aro.org, bhelgaas@...gle.com,
conor+dt@...nel.org, devicetree@...r.kernel.org, festevam@...il.com,
helgaas@...nel.org, hongxing.zhu@....com, imx@...ts.linux.dev,
kernel@...gutronix.de, krzysztof.kozlowski+dt@...aro.org,
kw@...ux.com, l.stach@...gutronix.de,
linux-arm-kernel@...ts.infradead.org, linux-imx@....com,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
lpieralisi@...nel.org, robh@...nel.org, s.hauer@...gutronix.de,
shawnguo@...nel.org
Subject: Re: [PATCH v8 07/16] PCI: imx6: Simplify configure_type() by using
mode_off and mode_mask
On Mon, Jan 08, 2024 at 06:21:36PM -0500, Frank Li wrote:
> Add drvdata::mode_off and drvdata::mode_mask to simplify
> imx6_pcie_configure_type() logic.
>
> Signed-off-by: Frank Li <Frank.Li@....com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
- Mani
> ---
>
> Notes:
> Change from v7 to v8
> - replace simple with simplify
> - remove reduntant comments about FILED_PREP
> Change from v3 to v7
> - none
> Change from v2 to v3
> - none
> Change from v1 to v2
> - use ffs() to fixe build error.
>
> Change from v2 to v3
> - none
> Change from v1 to v2
> - use ffs() to fixe build error.
>
> drivers/pci/controller/dwc/pci-imx6.c | 59 ++++++++++++++++++---------
> 1 file changed, 39 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 818e73157e724..fd83af238fa60 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -68,6 +68,7 @@ enum imx6_pcie_variants {
>
> #define IMX6_PCIE_MAX_CLKS 6
>
> +#define IMX6_PCIE_MAX_INSTANCES 2
> struct imx6_pcie_drvdata {
> enum imx6_pcie_variants variant;
> enum dw_pcie_device_mode mode;
> @@ -78,6 +79,8 @@ struct imx6_pcie_drvdata {
> const u32 clks_cnt;
> const u32 ltssm_off;
> const u32 ltssm_mask;
> + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
> + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
> };
>
> struct imx6_pcie {
> @@ -174,32 +177,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
>
> static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> {
> - unsigned int mask, val, mode;
> + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> + unsigned int mask, val, mode, id;
>
> - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
> + if (drvdata->mode == DW_PCIE_EP_TYPE)
> mode = PCI_EXP_TYPE_ENDPOINT;
> else
> mode = PCI_EXP_TYPE_ROOT_PORT;
>
> - switch (imx6_pcie->drvdata->variant) {
> - case IMX8MQ:
> - case IMX8MQ_EP:
> - if (imx6_pcie->controller_id == 1) {
> - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
> - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> - mode);
> - } else {
> - mask = IMX6Q_GPR12_DEVICE_TYPE;
> - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
> - }
> - break;
> - default:
> - mask = IMX6Q_GPR12_DEVICE_TYPE;
> - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
> - break;
> - }
> + id = imx6_pcie->controller_id;
> +
> + /* If mode_mask[id] is zero, means each controller have its individual gpr */
> + if (!drvdata->mode_mask[id])
> + id = 0;
> +
> + mask = drvdata->mode_mask[id];
> + val = mode << (ffs(mask) - 1);
>
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
> }
>
> static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
> @@ -1389,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> .ltssm_off = IOMUXC_GPR12,
> .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX6SX] = {
> .variant = IMX6SX,
> @@ -1400,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_axi),
> .ltssm_off = IOMUXC_GPR12,
> .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX6QP] = {
> .variant = IMX6QP,
> @@ -1412,6 +1411,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> .ltssm_off = IOMUXC_GPR12,
> .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX7D] = {
> .variant = IMX7D,
> @@ -1421,6 +1422,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx7d-iomuxc-gpr",
> .clk_names = imx6_3clks_bus_pcie_phy,
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX8MQ] = {
> .variant = IMX8MQ,
> @@ -1429,6 +1432,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> .clk_names = imx6_4clks_bus_pcie_phy_aux,
> .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .mode_off[1] = IOMUXC_GPR12,
> + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> },
> [IMX8MM] = {
> .variant = IMX8MM,
> @@ -1438,6 +1445,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> .clk_names = imx6_3clks_bus_pcie_aux,
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX8MP] = {
> .variant = IMX8MP,
> @@ -1447,6 +1456,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> .clk_names = imx6_3clks_bus_pcie_aux,
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX8MQ_EP] = {
> .variant = IMX8MQ_EP,
> @@ -1456,6 +1467,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> .clk_names = imx6_4clks_bus_pcie_phy_aux,
> .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .mode_off[1] = IOMUXC_GPR12,
> + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> },
> [IMX8MM_EP] = {
> .variant = IMX8MM_EP,
> @@ -1464,6 +1479,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> .clk_names = imx6_3clks_bus_pcie_aux,
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> @@ -1472,6 +1489,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> .clk_names = imx6_3clks_bus_pcie_aux,
> .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> + .mode_off[0] = IOMUXC_GPR12,
> + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> },
> };
>
> --
> 2.34.1
>
--
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