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Date: Fri, 19 Jan 2024 18:06:15 +0800
From: Tengfei Fan <quic_tengfan@...cinc.com>
To: <andersson@...nel.org>, <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<dmitry.baryshkov@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <kernel@...cinc.com>,
Tengfei Fan
<quic_tengfan@...cinc.com>
Subject: [PATCH v4 0/6] arm64: qcom: add AIM300 AIoT board support
Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
sound card and PMIC functions.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. The module is mounted onto Qualcomm AIoT
carrier board to support verification, evaluation and development. It
integrates QCS8550 SoC, UFS and PMIC chip etc.
Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
---
v3 -> v4:
- use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
of qcm8550, another board with qcm8550 will be added later
- add AIM300 AIoT board string in qcom.yaml file
- add sm8550 and qcm8550 fallback compatible
- add qcm8550 SoC id
- add reserved memory map codes in qcm8550.dtsi
- pm8010 and pmr73d are splited into carrier board DTS file. Because
the regulators which in pm8550, pm8550ve and pm8550vs are present
on the SoM. The regulators which in pm8010 and pmr73d are present
on the carrier board.
- stay VPH_PWR at qcs8550-aim300.dtsi file
+----------------------------------------+
|AIM300 SoM |
| |
| +-----+ |
| |--->| UFS | |
| | +-----+ |
| | |
| | |
3.7v | +-----------------+ | +---------+ |
---------->| PMIC |----->| QCS8550 | |
| +-----------------+ +---------+ |
| | |
| | |
| | +-----+ |
| |--->| ... | |
| +-----+ |
| |
+----------------------------------------+
VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
v2 -> v3:
- introduce qcs8550.dtsi
- separate fix dtc W=1 warning patch to another patch series
v1 -> v2:
- merge the splited dts patches into one patch
- update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
- drop PCIe1 dts node due to it is not enabled
- update display node name for drop sde characters
previous discussion here:
[1] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com
[2] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com
[3] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com
Tengfei Fan (6):
dt-bindings: arm: qcom: Document QCM8550, QCS8550 SoC and board
dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550
soc: qcom: socinfo: add SoC Info support for QCM8550 and QCS8550
platform
arm64: dts: qcom: qcm8550: introduce qcm8550 dtsi
arm64: dts: qcom: add base AIM300 dtsi
arm64: dts: qcom: aim300: add AIM300 AIoT
.../devicetree/bindings/arm/qcom.yaml | 11 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcm8550.dtsi | 170 +++++
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 600 ++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 368 +++++++++++
drivers/soc/qcom/socinfo.c | 2 +
include/dt-bindings/arm/qcom,ids.h | 2 +
7 files changed, 1154 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcm8550.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
base-commit: ad5c60d66016e544c51ed98635a74073f761f45d
--
2.17.1
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