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Message-ID: <CAMRc=MeatMgQqase263xfsLRcSwMjx3Xwprt78igooYT-+8NaQ@mail.gmail.com>
Date: Fri, 19 Jan 2024 12:53:28 +0100
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Cc: dlemoal@...nel.org, cassel@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linus.walleij@...aro.org, michal.simek@....com, p.zabel@...gutronix.de,
gregkh@...uxfoundation.org, piyush.mehta@....com, mubin.sayyed@....com,
linux-ide@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-usb@...r.kernel.org, git@....com
Subject: Re: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
On Fri, Jan 19, 2024 at 12:36 PM Radhey Shyam Pandey
<radhey.shyam.pandey@....com> wrote:
>
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
> ---
[snip]
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <piyush.mehta@....com>
> + - Mubin Sayyed <mubin.sayyed@....com>
> + - Radhey Shyam Pandey <radhey.shyam.pandey@....com>
>
> properties:
> compatible:
For GPIO:
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
[snip]
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