lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <003c8ea1-c455-4f68-bc8d-7ed9aa968a58@quicinc.com>
Date: Fri, 19 Jan 2024 09:59:37 -0800
From: Elliot Berman <quic_eberman@...cinc.com>
To: Andrew Halaney <ahalaney@...hat.com>,
        Maulik Shah
	<quic_mkshah@...cinc.com>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_collinsd@...cinc.com>, <quic_lsrao@...cinc.com>
Subject: Re: [PATCH v2] soc: qcom: rpmh-rsc: Enhance check for VREG in-flight
 request



On 1/19/2024 7:47 AM, Andrew Halaney wrote:
> On Fri, Jan 19, 2024 at 01:56:54PM +0530, Maulik Shah wrote:
>> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
>> addresses associated with it. These control voltage, enable state, mode,
>> and in legacy targets, voltage headroom. The current in-flight request
>> checking logic looks for exact address matches. Requests for different
>> addresses of the same RPMh resource as thus not detected as in-flight.
>>
>> Enhance the in-flight request check for VREG requests by ignoring the
>> address offset. This ensures that only one request is allowed to be
>> in-flight for a given VREG resource. This is needed to avoid scenarios
>> where request commands are carried out by RPMh hardware out-of-order
>> leading to LDO regulator over-current protection triggering.
>>
>> Signed-off-by: Maulik Shah <quic_mkshah@...cinc.com>
>> Signed-off-by: Elliot Berman <quic_eberman@...cinc.com>
> 
> Just noticed I commented on v1 when v2 was already out, sorry. Copy
> pasting this just to keep it on the latest thread:
> 
> Two minor things:
> 
>     1. Does this deserve a Fixes: tag?
>     2. The Signed-off-by chain here confuses me, you sent the patch
>        so your SOB should be last, but then that makes me believe Elliot
>        was the author which I don't think is reflected here (no From:
>        line). Please read [0] for a bit more details
> 
> [0] https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1
> 

Maulik's S-o-B should be last. This change was authored by him
in our downstream driver and this change was pointed out as
also being a fix for the upstream driver. I helped rebase/apply
the change to upstream to test and shared patch back with him
for posting to the list.

When he got the rebased patch, my S-o-B would've been last, but
now need to be updated again so his is last.

>> ---
>> Changes in v2:
>> - Use GENMASK() and FIELD_GET()
>> - Link to v1: https://lore.kernel.org/r/20240117-rpmh-rsc-fixes-v1-1-71ee4f8f72a4@quicinc.com
>> ---
>>  drivers/soc/qcom/rpmh-rsc.c | 21 ++++++++++++++++++++-
>>  1 file changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
>> index a021dc71807b..e480cde783fe 100644
>> --- a/drivers/soc/qcom/rpmh-rsc.c
>> +++ b/drivers/soc/qcom/rpmh-rsc.c
>> @@ -1,11 +1,13 @@
>>  // SPDX-License-Identifier: GPL-2.0
>>  /*
>>   * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>   */
>>  
>>  #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
>>  
>>  #include <linux/atomic.h>
>> +#include <linux/bitfield.h>
>>  #include <linux/cpu_pm.h>
>>  #include <linux/delay.h>
>>  #include <linux/interrupt.h>
>> @@ -91,6 +93,15 @@ enum {
>>  #define CMD_STATUS_ISSUED		BIT(8)
>>  #define CMD_STATUS_COMPL		BIT(16)
>>  
>> +#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)
>> +#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
>> +
>> +enum {
>> +	HW_ACCL_CLK = 0x3,
>> +	HW_ACCL_VREG,
>> +	HW_ACCL_BUS,
>> +};
>> +
>>  /*
>>   * Here's a high level overview of how all the registers in RPMH work
>>   * together:
>> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>>  		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>>  			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>>  			for (k = 0; k < msg->num_cmds; k++) {
>> -				if (addr == msg->cmds[k].addr)
>> +				/*
>> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
>> +				 * aligned addresses associated with it. Ignore the offset to check
>> +				 * for in-flight VREG requests.
>> +				 */
>> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
>> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
>> +					return -EBUSY;
>> +				else if (addr == msg->cmds[k].addr)
>>  					return -EBUSY;
>>  			}
>>  		}
>>
>> ---
>> base-commit: 943b9f0ab2cfbaea148dd6ac279957eb08b96904
>> change-id: 20240117-rpmh-rsc-fixes-6c43c7051828
>>
>> Best regards,
>> -- 
>> Maulik Shah <quic_mkshah@...cinc.com>
>>
>>
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ