linux-kernel - [PATCH v3 01/10] RISC-V: add helper function to read the vector VLEN

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Message-ID: <20240122002024.27477-2-ebiggers@kernel.org>
Date: Sun, 21 Jan 2024 16:19:12 -0800
From: Eric Biggers <ebiggers@...nel.org>
To: linux-crypto@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org,
	Albert Ou <aou@...s.berkeley.edu>,
	Andy Chiu <andy.chiu@...ive.com>,
	Ard Biesheuvel <ardb@...nel.org>,
	Christoph Müllner <christoph.muellner@...ll.eu>,
	Heiko Stuebner <heiko@...ech.de>,
	Jerry Shih <jerry.shih@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Phoebe Chen <phoebe.chen@...ive.com>,
	hongrong.hsu@...ive.com,
	Heiko Stuebner <heiko.stuebner@...ll.eu>
Subject: [PATCH v3 01/10] RISC-V: add helper function to read the vector VLEN

From: Heiko Stuebner <heiko.stuebner@...ll.eu>

VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.

The vector code already includes a variable riscv_v_vsize that contains
the value of "32 vector registers with vlenb length" that gets filled
during boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".

So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.

Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
Reviewed-by: Eric Biggers <ebiggers@...gle.com>
Signed-off-by: Jerry Shih <jerry.shih@...ive.com>
Signed-off-by: Eric Biggers <ebiggers@...gle.com>
---
 arch/riscv/include/asm/vector.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 0cd6f0a027d1f..731dcd0ed4de9 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -277,11 +277,22 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
 #define riscv_v_vstate_restore(vstate, regs)	do {} while (0)
 #define __switch_to_vector(__prev, __next)	do {} while (0)
 #define riscv_v_vstate_off(regs)		do {} while (0)
 #define riscv_v_vstate_on(regs)			do {} while (0)
 #define riscv_v_thread_free(tsk)		do {} while (0)
 #define  riscv_v_setup_ctx_cache()		do {} while (0)
 #define riscv_v_thread_alloc(tsk)		do {} while (0)
 
 #endif /* CONFIG_RISCV_ISA_V */
 
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+	return riscv_v_vsize / 32 * 8;
+}
+
 #endif /* ! __ASM_RISCV_VECTOR_H */
-- 
2.43.0