lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <069e3e67-fd93-4af4-905e-d4087a5b3153@kernel.org>
Date: Mon, 22 Jan 2024 19:28:53 +0900
From: Damien Le Moal <dlemoal@...nel.org>
To: Radhey Shyam Pandey <radhey.shyam.pandey@....com>, cassel@...nel.org,
 richardcochran@...il.com, piyush.mehta@...inx.com, axboe@...nel.dk,
 michal.simek@....com
Cc: linux-ide@...r.kernel.org, linux-kernel@...r.kernel.org, git@....com,
 Piyush Mehta <piyush.mehta@....com>
Subject: Re: [PATCH 1/2] ata: ahci_ceva: fix error handling for Xilinx GT PHY
 support

On 1/19/24 04:08, Radhey Shyam Pandey wrote:
> From: Piyush Mehta <piyush.mehta@....com>
> 
> Platform clock and phy error resources are not cleaned up in Xilinx GT PHY
> error path. To fix introduce error label for ahci_platform_disable_clks and
> phy_power_off/exit and call them in error path. No functional change.
> 
> Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy")
> Signed-off-by: Piyush Mehta <piyush.mehta@....com>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
> ---
> ---

Your patch format is strange... There is one too many "---" line here.

Other than that, looks OK to me.

Reviewed-by: Damien Le Moal <dlemoal@...nel.org>


-- 
Damien Le Moal
Western Digital Research


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ