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Message-ID: <20240123025613.3976-1-zhifeng.tang@unisoc.com>
Date: Tue, 23 Jan 2024 10:56:10 +0800
From: Zhifeng Tang <zhifeng.tang@...soc.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Orson Zhai <orsonzhai@...il.com>,
Baolin Wang
<baolin.wang@...ux.alibaba.com>,
Chunyan Zhang <zhang.lyra@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Zhifeng Tang <zhifeng.tang23@...il.com>,
Wenming Wu <wenming.wu@...soc.com>
Subject: [PATCH V4 0/3] Add reset controller driver for ums512
From: "zhifeng.tang" <zhifeng.tang@...soc.com>
In most of Sprd SOCs,The clock controller register block also
contains reset bits for some of these peripherals,so reset
controller and clock provider are combined together as a block,
and put it under the driver/clk/.
Changes in v4:
- Add description why reset controller put it under the driver/clk/
Changes in v3:
- Fix the driver patch is overwritten by cover letter
Changes in v2:
- The binding file is combined into one patch
zhifeng.tang (3):
dt-bindings: reset: Add reset controller bindings for Unisoc's ums512
clk: sprd: Add reset controller driver for ums512
arm64: dts: sprd: Add reset controller driver for UMS512
.../bindings/clock/sprd,ums512-clk.yaml | 3 +
arch/arm64/boot/dts/sprd/ums512.dtsi | 9 +
drivers/clk/sprd/Makefile | 1 +
drivers/clk/sprd/common.c | 1 +
drivers/clk/sprd/common.h | 2 +
drivers/clk/sprd/reset.c | 78 ++++++
drivers/clk/sprd/reset.h | 30 +++
drivers/clk/sprd/ums512-clk.c | 240 ++++++++++++++++++
include/dt-bindings/reset/sprd,ums512-reset.h | 203 +++++++++++++++
9 files changed, 567 insertions(+)
create mode 100644 drivers/clk/sprd/reset.c
create mode 100644 drivers/clk/sprd/reset.h
create mode 100644 include/dt-bindings/reset/sprd,ums512-reset.h
--
2.17.1
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