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Message-ID: <87r0i7kvh7.fsf@intel.com> Date: Wed, 24 Jan 2024 10:04:52 +0200 From: Jani Nikula <jani.nikula@...ux.intel.com> To: Lucas De Marchi <lucas.demarchi@...el.com>, Yury Norov <yury.norov@...il.com> Cc: linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org, Andy Shevchenko <andriy.shevchenko@...ux.intel.com>, intel-xe@...ts.freedesktop.org, intel-gfx@...ts.freedesktop.org, Lucas De Marchi <lucas.demarchi@...el.com> Subject: Re: [PATCH 3/3] drm/i915: Convert REG_GENMASK* to fixed-width GENMASK_* On Tue, 23 Jan 2024, Lucas De Marchi <lucas.demarchi@...el.com> wrote: > Now that include/linux/bits.h implements fixed-width GENMASK_*, use them > to implement the i915/xe specific macros. Converting each driver to use > the generic macros are left for later, when/if other driver-specific > macros are also generalized. With the type-specific max checks added to GENMASK_*, this would be great. BR, Jani. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@...el.com> > --- > drivers/gpu/drm/i915/i915_reg_defs.h | 108 +++------------------------ > 1 file changed, 11 insertions(+), 97 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h > index a685db1e815d..52f99eb96f86 100644 > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > @@ -9,76 +9,19 @@ > #include <linux/bitfield.h> > #include <linux/bits.h> > > -/** > - * REG_BIT() - Prepare a u32 bit value > - * @__n: 0-based bit number > - * > - * Local wrapper for BIT() to force u32, with compile time checks. > - * > - * @return: Value with bit @__n set. > - */ > -#define REG_BIT(__n) \ > - ((u32)(BIT(__n) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ > - ((__n) < 0 || (__n) > 31)))) > - > -/** > - * REG_BIT8() - Prepare a u8 bit value > - * @__n: 0-based bit number > - * > - * Local wrapper for BIT() to force u8, with compile time checks. > - * > - * @return: Value with bit @__n set. > - */ > -#define REG_BIT8(__n) \ > - ((u8)(BIT(__n) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ > - ((__n) < 0 || (__n) > 7)))) > - > -/** > - * REG_GENMASK() - Prepare a continuous u32 bitmask > - * @__high: 0-based high bit > - * @__low: 0-based low bit > - * > - * Local wrapper for GENMASK() to force u32, with compile time checks. > - * > - * @return: Continuous bitmask from @__high to @__low, inclusive. > - */ > -#define REG_GENMASK(__high, __low) \ > - ((u32)(GENMASK(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) > - > -/** > - * REG_GENMASK64() - Prepare a continuous u64 bitmask > - * @__high: 0-based high bit > - * @__low: 0-based low bit > - * > - * Local wrapper for GENMASK_ULL() to force u64, with compile time checks. > - * > - * @return: Continuous bitmask from @__high to @__low, inclusive. > +/* > + * Wrappers over the generic BIT_* and GENMASK_* implementations, > + * for compatibility reasons with previous implementation > */ > -#define REG_GENMASK64(__high, __low) \ > - ((u64)(GENMASK_ULL(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 63 || (__low) > (__high))))) > +#define REG_GENMASK(__high, __low) GENMASK_U32(__high, __low) > +#define REG_GENMASK64(__high, __low) GENMASK_U64(__high, __low) > +#define REG_GENMASK16(__high, __low) GENMASK_U16(__high, __low) > +#define REG_GENMASK8(__high, __low) GENMASK_U8(__high, __low) > > -/** > - * REG_GENMASK8() - Prepare a continuous u8 bitmask > - * @__high: 0-based high bit > - * @__low: 0-based low bit > - * > - * Local wrapper for GENMASK() to force u8, with compile time checks. > - * > - * @return: Continuous bitmask from @__high to @__low, inclusive. > - */ > -#define REG_GENMASK8(__high, __low) \ > - ((u8)(GENMASK(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 7 || (__low) > (__high))))) > +#define REG_BIT(__n) BIT_U32(__n) > +#define REG_BIT64(__n) BIT_U64(__n) > +#define REG_BIT16(__n) BIT_U16(__n) > +#define REG_BIT8(__n) BIT_U8(__n) > > /* > * Local integer constant expression version of is_power_of_2(). > @@ -143,35 +86,6 @@ > */ > #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) > > -/** > - * REG_BIT16() - Prepare a u16 bit value > - * @__n: 0-based bit number > - * > - * Local wrapper for BIT() to force u16, with compile time > - * checks. > - * > - * @return: Value with bit @__n set. > - */ > -#define REG_BIT16(__n) \ > - ((u16)(BIT(__n) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ > - ((__n) < 0 || (__n) > 15)))) > - > -/** > - * REG_GENMASK16() - Prepare a continuous u8 bitmask > - * @__high: 0-based high bit > - * @__low: 0-based low bit > - * > - * Local wrapper for GENMASK() to force u16, with compile time > - * checks. > - * > - * @return: Continuous bitmask from @__high to @__low, inclusive. > - */ > -#define REG_GENMASK16(__high, __low) \ > - ((u16)(GENMASK(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 15 || (__low) > (__high))))) > > /** > * REG_FIELD_PREP16() - Prepare a u16 bitfield value -- Jani Nikula, Intel
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