lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240124122936.816142-1-s-vadapalli@ti.com>
Date: Wed, 24 Jan 2024 17:59:36 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
        <robh@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <vigneshr@...com>, <afd@...com>, <srk@...com>, <s-vadapalli@...com>
Subject: [PATCH v3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
The controller on J722S SoC is similar to the one present on TI's AM64
SoC, with the difference being that the controller on AM64 SoC supports
up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.

Update the bindings with a new compatible for J722S SoC.

Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3

Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
---

Hello,

This patch is based on linux-next tagged next-20240124.

v2:
https://lore.kernel.org/r/20240122064457.664542-1-s-vadapalli@ti.com/
Changes since v2:
- Added fallback compatible for "ti,j722s-pcie-host" as
  "ti,j721e-pcie-host" based on Conor's suggestion at:
  https://lore.kernel.org/r/20240122-getting-drippy-bb22a0634092@spud/#t

v1:
https://lore.kernel.org/r/20240117102526.557006-1-s-vadapalli@ti.com/
Changes since v1:
- Dropped patches 1/3 and 2/3 of the v1 series as discussed in the v1
  thread.
- Updated patch 3/3 which is the v1 for this patch by dropping the checks
  for the "num-lanes" property and "max-link-speed" property since the PCI
  driver already validates the "num-lanes" property.

Regards,
Siddharth.

 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index b7a534cef24d..ac69deeaf1ee 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -23,6 +23,10 @@ properties:
         items:
           - const: ti,j7200-pcie-host
           - const: ti,j721e-pcie-host
+      - description: PCIe controller in J722S
+        items:
+          - const: ti,j722s-pcie-host
+          - const: ti,j721e-pcie-host
 
   reg:
     maxItems: 4
-- 
2.34.1


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ