linux-kernel - [PATCH v2 4/4] riscv: dts: add resets property for uart node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <685eeea20960d96ac2c37eb8990e1f7112ee4178.1706161530.git.unicorn_wang@outlook.com>
Date: Thu, 25 Jan 2024 14:11:58 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu,
	chao.wei@...hgo.com,
	conor@...nel.org,
	krzysztof.kozlowski+dt@...aro.org,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	p.zabel@...gutronix.de,
	robh+dt@...nel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	haijiao.liu@...hgo.com,
	xiaoguang.xing@...hgo.com,
	guoren@...nel.org,
	jszhang@...nel.org,
	inochiama@...look.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH v2 4/4] riscv: dts: add resets property for uart node

From: Chen Wang <unicorn_wang@...look.com>

Add resets property for uart0 for completeness, although it is
deasserted by default.

Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index f59081d4f0ee..03266f216021 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -327,6 +327,7 @@ uart0: serial@...0000000 {
 			clock-frequency = <500000000>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			resets = <&rstgen RST_UART0>;
 			status = "disabled";
 		};
 	};
-- 
2.25.1