linux-kernel - Re: [PATCH v3 3/3] dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format

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Date: Thu, 25 Jan 2024 08:27:55 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: <Dharma.B@...rochip.com>
CC: <conor@...nel.org>, <sam@...nborg.org>, <bbrezillon@...nel.org>,
	<maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
	<tzimmermann@...e.de>, <airlied@...il.com>, <daniel@...ll.ch>,
	<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
	<conor+dt@...nel.org>, <Nicolas.Ferre@...rochip.com>,
	<alexandre.belloni@...tlin.com>, <claudiu.beznea@...on.dev>,
	<dri-devel@...ts.freedesktop.org>, <devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
	<lee@...nel.org>, <thierry.reding@...il.com>,
	<u.kleine-koenig@...gutronix.de>, <linux-pwm@...r.kernel.org>,
	<Linux4Microchip@...rochip.com>
Subject: Re: [PATCH v3 3/3] dt-bindings: mfd: atmel,hlcdc: Convert to DT
 schema format


> > If the lvds pll is an input to the hlcdc, you need to add it here.
> >  From your description earlier it does sound like it is an input to
> > the hlcdc, but now you are claiming that it is not.
> 
> The LVDS PLL serves as an input to both the LCDC and LVDSC

Then it should be an input to both the LCDC and LVDSC in the devicetree.

> with the 
> LVDS_PLL multiplied by 7 for the Pixel clock to the LVDS PHY, and 

Are you sure? The diagram doesn't show a multiplier, the 7x comment
there seems to be showing relations?

> LVDS_PLL divided by 7 for the Pixel clock to the LCDC.

> I am inclined to believe that appropriately configuring and enabling it 
> in the LVDS driver would be the appropriate course of action.

We're talking about bindings here, not drivers, but I would imagine that
if two peripherals are using the same clock then both of them should be
getting a reference to and enabling that clock so that the clock
framework can correctly track the users.

> > I don't know your hardware, so I have no idea which of the two is
> > correct, but it sounds like the former. Without digging into how this
> > works my assumption about the hardware here looks like is that the lvds
> > controller is a clock provider,
> 
> It's a PLL clock from PMC.
> 
> > and that the lvds controller's clock is
> > an optional input for the hlcdc.
> 
> Again it's a PLL clock from PMC.
> 
> Please refer Section 39.3 
> https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ProductDocuments/DataSheets/SAM9X7-Series-Data-Sheet-DS60001813.pdf

It is not the same exact clock as you pointed out above though, so the
by 7 divider should be modelled.

> > Can you please explain what provides the lvds pll clock and show an
> > example of how you think the devictree would look with "the lvds pll in
> > the lvds dt node"?
> 
> Sure, Please see the below example
> 
> The typical lvds node will look like
> 
>                  lvds_controller: lvds-controller@...60000 {
>                          compatible = "microchip,sam9x7-lvds";
>                          reg = <0xf8060000 0x100>;
>                          interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>;
>                          clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc 
> PMC_TYPE_CORE PMC_LVDSPLL>;
>                          clock-names = "pclk", "lvds_pll_clk";
>                          status = "disabled";
>                  };

In isolation, this looks fine.

Cheers,
Conor.

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