lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <c06b02b1-f04a-497c-a84b-2516f160e8a5@linaro.org>
Date: Thu, 25 Jan 2024 13:35:53 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konrad.dybcio@...aro.org>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof WilczyƄski <kw@...ux.com>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
 linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to
 dedicated schema

On 17/01/2024 07:30, Manivannan Sadhasivam wrote:
>>
>> How does a given SoC have 1 or 8 interrupts? I guess it is possible. A 
>> comment here would be helpful.
>>
> 
> No, this is due to kernel developers not able to find out the max MSI numbers
> for each platforms out of the Qcom internal documentation.
> 
> Let it be for now, I will try to fetch these numbers to make it accurate later.

I'll complete the interrupts the binding and the DTS.

Best regards,
Krzysztof


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ