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Message-ID: <8cdbf784-e094-45f2-89dd-a2c58cf408ef@linaro.org>
Date: Fri, 26 Jan 2024 08:51:03 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: Mark Brown <broonie@...nel.org>,
Sam Protsenko <semen.protsenko@...aro.org>
Cc: andi.shyti@...nel.org, arnd@...db.de, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
alim.akhtar@...sung.com, linux-spi@...r.kernel.org,
linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-arch@...r.kernel.org, andre.draszik@...aro.org,
peter.griffin@...aro.org, kernel-team@...roid.com, willmcvicker@...gle.com
Subject: Re: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX,
TX}_FIFO_LVL
On 1/25/24 21:48, Mark Brown wrote:
> On Thu, Jan 25, 2024 at 02:03:15PM -0600, Sam Protsenko wrote:
>> On Thu, Jan 25, 2024 at 8:50 AM Tudor Ambarus <tudor.ambarus@...aro.org> wrote:
>
>>> +#define S3C64XX_SPI_ST_RX_FIFO_LVL GENMASK(23, 15)
>
>> What about s3c* architectures, where RX_LVL starts with bit #13, as
>> can be seen from .rx_lvl_offset values in corresponding port_configs?
>> Wouldn't this change break those?
>
> I should point out that I have a s3c6410 board I care about.
Obviously, I don't want to break things, but it may happen as Sam
pointed out. I'll be around to fix whatever I break. It's good that you
have a s3c6410 board, maybe you can run a test on it after I send v3?
Thanks!
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