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Message-Id: <20240126085444.324918-23-xiong.y.zhang@linux.intel.com> Date: Fri, 26 Jan 2024 16:54:25 +0800 From: Xiong Zhang <xiong.y.zhang@...ux.intel.com> To: seanjc@...gle.com, pbonzini@...hat.com, peterz@...radead.org, mizhang@...gle.com, kan.liang@...el.com, zhenyuw@...ux.intel.com, dapeng1.mi@...ux.intel.com, jmattson@...gle.com Cc: kvm@...r.kernel.org, linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org, zhiyuan.lv@...el.com, eranian@...gle.com, irogers@...gle.com, samantha.alt@...el.com, like.xu.linux@...il.com, chao.gao@...el.com, xiong.y.zhang@...ux.intel.com Subject: [RFC PATCH 22/41] x86: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET for passthrough PMU From: Dapeng Mi <dapeng1.mi@...ux.intel.com> Add additional PMU MSRs MSR_CORE_PERF_GLOBAL_STATUS_SET to allow passthrough PMU operation on the read-only MSR IA32_PERF_GLOBAL_STATUS. Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com> Signed-off-by: Mingwei Zhang <mizhang@...gle.com> --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1d51e1850ed0..270f4f420801 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1059,6 +1059,7 @@ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 #define MSR_PERF_METRICS 0x00000329 -- 2.34.1
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