linux-kernel - [PATCH v2 06/15] phy: ti: phy-j721e-wiz: make wiz_clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20240102-j7200-pcie-s2r-v2-6-8e4f7d228ec2@bootlin.com>
Date: Fri, 26 Jan 2024 15:36:48 +0100
From: Thomas Richard <thomas.richard@...tlin.com>
To: Linus Walleij <linus.walleij@...aro.org>, 
 Bartosz Golaszewski <brgl@...ev.pl>, Andy Shevchenko <andy@...nel.org>, 
 Tony Lindgren <tony@...mide.com>, 
 Haojian Zhuang <haojian.zhuang@...aro.org>, Vignesh R <vigneshr@...com>, 
 Aaro Koskinen <aaro.koskinen@....fi>, 
 Janusz Krzysztofik <jmkrzyszt@...il.com>, 
 Andi Shyti <andi.shyti@...nel.org>, Peter Rosin <peda@...ntia.se>, 
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, 
 Philipp Zabel <p.zabel@...gutronix.de>, Tom Joseph <tjoseph@...ence.com>, 
 Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof Wilczyński <kw@...ux.com>, 
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>
Cc: linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-arm-kernel@...ts.infradead.org, linux-omap@...r.kernel.org, 
 linux-i2c@...r.kernel.org, linux-phy@...ts.infradead.org, 
 linux-pci@...r.kernel.org, gregory.clement@...tlin.com, 
 theo.lebrun@...tlin.com, thomas.petazzoni@...tlin.com, u-kumar1@...com, 
 Thomas Richard <thomas.richard@...tlin.com>
Subject: [PATCH v2 06/15] phy: ti: phy-j721e-wiz: make wiz_clock_init
 callable multiple times

For suspend and resume support, wiz_clock_init needs to be called multiple
times.

Add a parameter to wiz_clock_init to be able to skip clocks registration.

Based on the work of Théo Lebrun <theo.lebrun@...tlin.com>

Signed-off-by: Thomas Richard <thomas.richard@...tlin.com>
---
 drivers/phy/ti/phy-j721e-wiz.c | 60 +++++++++++++++++++++++++-----------------
 1 file changed, 36 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index fc3cd98c60ff..09f7edf16562 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -1076,7 +1076,7 @@ static int wiz_clock_register(struct wiz *wiz)
 	return ret;
 }
 
-static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
+static int wiz_clock_init(struct wiz *wiz, struct device_node *node, bool probe)
 {
 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 	struct device *dev = wiz->dev;
@@ -1087,14 +1087,36 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 	int ret;
 	int i;
 
-	clk = devm_clk_get(dev, "core_ref_clk");
-	if (IS_ERR(clk)) {
-		dev_err(dev, "core_ref_clk clock not found\n");
-		ret = PTR_ERR(clk);
-		return ret;
+	if (probe) {
+		clk = devm_clk_get(dev, "core_ref_clk");
+		if (IS_ERR(clk)) {
+			dev_err(dev, "core_ref_clk clock not found\n");
+			ret = PTR_ERR(clk);
+			return ret;
+		}
+		wiz->input_clks[WIZ_CORE_REFCLK] = clk;
+
+		if (wiz->data->pma_cmn_refclk1_int_mode) {
+			clk = devm_clk_get(dev, "core_ref1_clk");
+			if (IS_ERR(clk)) {
+				dev_err(dev, "core_ref1_clk clock not found\n");
+				ret = PTR_ERR(clk);
+				return ret;
+			}
+			wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+		}
+
+		clk = devm_clk_get(dev, "ext_ref_clk");
+		if (IS_ERR(clk)) {
+			dev_err(dev, "ext_ref_clk clock not found\n");
+			ret = PTR_ERR(clk);
+			return ret;
+		}
+		wiz->input_clks[WIZ_EXT_REFCLK] = clk;
 	}
-	wiz->input_clks[WIZ_CORE_REFCLK] = clk;
 
+
+	clk = wiz->input_clks[WIZ_CORE_REFCLK];
 	rate = clk_get_rate(clk);
 	if (rate >= 100000000)
 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
@@ -1121,14 +1143,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 	}
 
 	if (wiz->data->pma_cmn_refclk1_int_mode) {
-		clk = devm_clk_get(dev, "core_ref1_clk");
-		if (IS_ERR(clk)) {
-			dev_err(dev, "core_ref1_clk clock not found\n");
-			ret = PTR_ERR(clk);
-			return ret;
-		}
-		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
-
+		clk = wiz->input_clks[WIZ_CORE_REFCLK1];
 		rate = clk_get_rate(clk);
 		if (rate >= 100000000)
 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
@@ -1136,20 +1151,17 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
 	}
 
-	clk = devm_clk_get(dev, "ext_ref_clk");
-	if (IS_ERR(clk)) {
-		dev_err(dev, "ext_ref_clk clock not found\n");
-		ret = PTR_ERR(clk);
-		return ret;
-	}
-	wiz->input_clks[WIZ_EXT_REFCLK] = clk;
-
+	clk = wiz->input_clks[WIZ_EXT_REFCLK];
 	rate = clk_get_rate(clk);
 	if (rate >= 100000000)
 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
 	else
 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
 
+	/* What follows is about registering clocks. */
+	if (!probe)
+		return 0;
+
 	switch (wiz->type) {
 	case AM64_WIZ_10G:
 	case J7200_WIZ_10G:
@@ -1592,7 +1604,7 @@ static int wiz_probe(struct platform_device *pdev)
 		goto err_get_sync;
 	}
 
-	ret = wiz_clock_init(wiz, node);
+	ret = wiz_clock_init(wiz, node, true);
 	if (ret < 0) {
 		dev_warn(dev, "Failed to initialize clocks\n");
 		goto err_get_sync;

-- 
2.39.2