linux-kernel - [RFC v1 2/2] riscv: cacheinfo: Refactor populate_cache

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Message-Id: <20240129075957.116033-3-jeeheng.sia@starfivetech.com>
Date: Sun, 28 Jan 2024 23:59:57 -0800
From: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
To: linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Cc: paul.walmsley@...ive.com,
	palmer@...belt.com,
	aou@...s.berkeley.edu,
	sudeep.holla@....com,
	jeeheng.sia@...rfivetech.com,
	robh@...nel.org,
	conor.dooley@...rochip.com,
	suagrfillet@...il.com
Subject: [RFC v1 2/2] riscv: cacheinfo: Refactor populate_cache_leaves()

Refactoring the cache population function to support both DT and
ACPI-based platforms.

Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
---
 arch/riscv/kernel/cacheinfo.c | 47 ++++++++++++++---------------------
 1 file changed, 19 insertions(+), 28 deletions(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 30a6878287ad..f10e26fb75b6 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -74,36 +74,27 @@ int populate_cache_leaves(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
-	struct device_node *np = of_cpu_device_node_get(cpu);
-	struct device_node *prev = NULL;
-	int levels = 1, level = 1;
-
-	if (of_property_read_bool(np, "cache-size"))
-		ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
-	if (of_property_read_bool(np, "i-cache-size"))
-		ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
-	if (of_property_read_bool(np, "d-cache-size"))
-		ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
-
-	prev = np;
-	while ((np = of_find_next_cache_node(np))) {
-		of_node_put(prev);
-		prev = np;
-		if (!of_device_is_compatible(np, "cache"))
-			break;
-		if (of_property_read_u32(np, "cache-level", &level))
-			break;
-		if (level <= levels)
-			break;
-		if (of_property_read_bool(np, "cache-size"))
-			ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
-		if (of_property_read_bool(np, "i-cache-size"))
-			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
-		if (of_property_read_bool(np, "d-cache-size"))
+	unsigned int level, idx;
+
+	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
+	     idx < this_cpu_ci->num_leaves; idx++, level++) {
+		/*
+		 * Since the RISC-V architecture doesn't provide any register for detecting the
+		 * Cache Level and Cache type, this assumes that:
+		 * - There cannot be any split caches (data/instruction) above a unified cache.
+		 * - Data/instruction caches come in pairs.
+		 * - Significant work is required elsewhere to fully support data/instruction-only
+		 *   type caches.
+		 * - The above assumptions are based on conventional system design and known
+		 *   examples.
+		 */
+		if (level == 1) {
 			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
-		levels = level;
+			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+		} else {
+			ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+		}
 	}
-	of_node_put(np);
 
 	return 0;
 }
-- 
2.34.1