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Message-ID: <CAEEQ3wmVT_Lo3Jsoj-yp-3RCEfu=D7QKJq110sN-2a-wV+R59w@mail.gmail.com>
Date: Mon, 29 Jan 2024 09:29:12 +0800
From: yunhui cui <cuiyunhui@...edance.com>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, 
	alexghiti@...osinc.com, samuel.holland@...ive.com, ajones@...tanamicro.com, 
	mchitale@...tanamicro.com, dylan@...estech.com, 
	sergey.matyukevich@...tacore.com, prabhakar.mahadev-lad.rj@...renesas.com, 
	jszhang@...nel.org, apatel@...tanamicro.com, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [External] Re: [PATCH] RISC-V: add uniprocessor flush_tlb_range() support

Hi Prabhakar,

On Sat, Jan 27, 2024 at 1:42 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
>
> On Thu, Jan 25, 2024 at 6:23 AM Yunhui Cui <cuiyunhui@...edance.com> wrote:
> >
> > Add support for flush_tlb_range() to improve TLB performance for
> > UP systems. In order to avoid the mutual inclusion of tlbflush.h
> > and hugetlb.h, the UP part is also implemented in tlbflush.c.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> > ---
> >  arch/riscv/include/asm/tlbflush.h |  61 ++++++----
> >  arch/riscv/mm/Makefile            |   2 +-
> >  arch/riscv/mm/tlbflush.c          | 195 ++++++++++++++++++------------
> >  3 files changed, 156 insertions(+), 102 deletions(-)
> >
> Boot tested with defconfig + rz/five enabled, no issues seen on
> RZ/Five SMARC EVK.
>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>

Thank you for testing !

Thanks,
Yunhui

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