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Message-ID: <CADrjBPrB1asSBxLe9wEfjbaNcEqz_3sXEu_3zfv=fTSk65o2sg@mail.gmail.com>
Date: Mon, 29 Jan 2024 09:20:01 +0000
From: Peter Griffin <peter.griffin@...aro.org>
To: André Draszik <andre.draszik@...aro.org>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linux-kernel@...r.kernel.org, kernel-team@...roid.com,
tudor.ambarus@...aro.org, willmcvicker@...gle.com, semen.protsenko@...aro.org,
alim.akhtar@...sung.com, s.nawrocki@...sung.com, tomasz.figa@...il.com,
cw00.choi@...sung.com, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH 4/9] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
On Sat, 27 Jan 2024 at 00:19, André Draszik <andre.draszik@...aro.org> wrote:
>
> Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
> and PWM interfaces / busses.
>
> Signed-off-by: André Draszik <andre.draszik@...aro.org>
> ---
Reviewed-by: Peter Griffin <peter.griffin@...aro.org>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index aaac04df5e65..5088c81fd6aa 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -429,6 +429,16 @@ serial_0: serial@...00000 {
> };
> };
>
> + cmu_peric1: clock-controller@...00000 {
> + compatible = "google,gs101-cmu-peric1";
> + reg = <0x10c00000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
> + clock-names = "oscclk", "bus", "ip";
> + };
> +
> sysreg_peric1: syscon@...20000 {
> compatible = "google,gs101-peric1-sysreg", "syscon";
> reg = <0x10c20000 0x10000>;
> --
> 2.43.0.429.g432eaa2c6b-goog
>
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