[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240129092553.2058043-6-peterlin@andestech.com>
Date: Mon, 29 Jan 2024 17:25:48 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <acme@...nel.org>, <adrian.hunter@...el.com>, <ajones@...tanamicro.com>,
<alexander.shishkin@...ux.intel.com>, <andre.przywara@....com>,
<anup@...infault.org>, <aou@...s.berkeley.edu>,
<atishp@...shpatra.org>, <conor+dt@...nel.org>,
<conor.dooley@...rochip.com>, <conor@...nel.org>,
<devicetree@...r.kernel.org>, <evan@...osinc.com>,
<geert+renesas@...der.be>, <guoren@...nel.org>, <heiko@...ech.de>,
<irogers@...gle.com>, <jernej.skrabec@...il.com>, <jolsa@...nel.org>,
<jszhang@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-perf-users@...r.kernel.org>,
<linux-renesas-soc@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-sunxi@...ts.linux.dev>, <locus84@...estech.com>,
<magnus.damm@...il.com>, <mark.rutland@....com>, <mingo@...hat.com>,
<n.shubin@...ro.com>, <namhyung@...nel.org>, <palmer@...belt.com>,
<paul.walmsley@...ive.com>, <peterlin@...estech.com>,
<peterz@...radead.org>, <prabhakar.mahadev-lad.rj@...renesas.com>,
<rdunlap@...radead.org>, <robh+dt@...nel.org>, <samuel@...lland.org>,
<sunilvl@...tanamicro.com>, <tglx@...utronix.de>,
<tim609@...estech.com>, <uwu@...nowy.me>, <wens@...e.org>,
<will@...nel.org>, <inochiama@...look.com>, <unicorn_wang@...look.com>,
<wefu@...hat.com>
Subject: [PATCH v8 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- Include Geert's Reviewed-by
- Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a92cfcfc021b..099f3df75b42 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -39,7 +39,7 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
--
2.34.1
Powered by blists - more mailing lists