linux-kernel - [PATCH v8 08/10] dt-bindings: riscv: Add Andes PMU extension description

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Message-ID: <20240129092553.2058043-9-peterlin@andestech.com>
Date: Mon, 29 Jan 2024 17:25:51 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <acme@...nel.org>, <adrian.hunter@...el.com>, <ajones@...tanamicro.com>,
        <alexander.shishkin@...ux.intel.com>, <andre.przywara@....com>,
        <anup@...infault.org>, <aou@...s.berkeley.edu>,
        <atishp@...shpatra.org>, <conor+dt@...nel.org>,
        <conor.dooley@...rochip.com>, <conor@...nel.org>,
        <devicetree@...r.kernel.org>, <evan@...osinc.com>,
        <geert+renesas@...der.be>, <guoren@...nel.org>, <heiko@...ech.de>,
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        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
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Subject: [PATCH v8 08/10] dt-bindings: riscv: Add Andes PMU extension description

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
Changes v2 -> v3:
  - New patch
Changes v3 -> v4:
  - Include Conor's Acked-by
Changes v4 -> v5:
  - Include Prabhakar's Reviewed-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
Changes v7 -> v8:
  - No change
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895e5..468c646247aa 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,12 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        - const: xandespmu
+          description:
+            The Andes Technology performance monitor extension for counter overflow
+            and privilege mode filtering. For more details, see Counter Related
+            Registers in the AX45MP datasheet.
+            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
 additionalProperties: true
 ...
-- 
2.34.1