linux-kernel - Re: [PATCH V16 2/8] KVM: arm64: Prevent guest accesses into BRBE system registers/instructions

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Message-ID: <4395415b-dfb1-4dd1-9dfd-181f0549be7c@arm.com>
Date: Tue, 30 Jan 2024 09:10:23 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 will@...nel.org, catalin.marinas@....com, mark.rutland@....com
Cc: Mark Brown <broonie@...nel.org>, James Clark <james.clark@....com>,
 Rob Herring <robh@...nel.org>, Marc Zyngier <maz@...nel.org>,
 Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
 Arnaldo Carvalho de Melo <acme@...nel.org>,
 linux-perf-users@...r.kernel.org, Oliver Upton <oliver.upton@...ux.dev>,
 James Morse <james.morse@....com>, kvmarm@...ts.linux.dev
Subject: Re: [PATCH V16 2/8] KVM: arm64: Prevent guest accesses into BRBE
 system registers/instructions



On 1/29/24 17:45, Suzuki K Poulose wrote:
> On 25/01/2024 09:41, Anshuman Khandual wrote:
>> Currently BRBE feature is not supported in a guest environment. This hides
>> BRBE feature availability via masking ID_AA64DFR0_EL1.BRBE field. This also
>> blocks guest accesses into BRBE system registers and instructions as if the
>> underlying hardware never implemented FEAT_BRBE feature.
>>
>> Cc: Marc Zyngier <maz@...nel.org>
>> Cc: Oliver Upton <oliver.upton@...ux.dev>
>> Cc: James Morse <james.morse@....com>
>> Cc: Suzuki K Poulose <suzuki.poulose@....com>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will@...nel.org>
>> Cc: kvmarm@...ts.linux.dev
>> Cc: linux-arm-kernel@...ts.infradead.org
>> Cc: linux-kernel@...r.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
>> ---
>> Changes in V16:
>>
>> - Added BRB_INF_SRC_TGT_EL1 macro for corresponding BRB_[INF|SRC|TGT] expansion
>>
>>   arch/arm64/kvm/sys_regs.c | 56 +++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 56 insertions(+)
>>
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 30253bd19917..6a06dc2f0c06 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1304,6 +1304,11 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
>>       return 0;
>>   }
>>   +#define BRB_INF_SRC_TGT_EL1(n)                    \
>> +    { SYS_DESC(SYS_BRBINF##n##_EL1), undef_access },    \
>> +    { SYS_DESC(SYS_BRBSRC##n##_EL1), undef_access },    \
>> +    { SYS_DESC(SYS_BRBTGT##n##_EL1), undef_access }        \
>> +
>>   /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
>>   #define DBG_BCR_BVR_WCR_WVR_EL1(n)                    \
>>       { SYS_DESC(SYS_DBGBVRn_EL1(n)),                    \
>> @@ -1707,6 +1712,9 @@ static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
>>       /* Hide SPE from guests */
>>       val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
>>   +    /* Hide BRBE from guests */
>> +    val &= ~ID_AA64DFR0_EL1_BRBE_MASK;
>> +
>>       return val;
>>   }
>>   @@ -2195,6 +2203,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>>       { SYS_DESC(SYS_DC_CISW), access_dcsw },
>>       { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
>>       { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
>> +    { SYS_DESC(OP_BRB_IALL), undef_access },
>> +    { SYS_DESC(OP_BRB_INJ), undef_access },
>>   
> 
> heads up: This may conflict with Marc's patches to move the sys instructions to a separate table. But otherwise, looks good to me.

Sure, will rebase this on recent changes.