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Message-Id: <20240130055843.216342-1-changhuang.liang@starfivetech.com>
Date: Mon, 29 Jan 2024 21:58:41 -0800
From: Changhuang Liang <changhuang.liang@...rfivetech.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>
Cc: Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
Jack Zhu <jack.zhu@...rfivetech.com>,
Changhuang Liang <changhuang.liang@...rfivetech.com>,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: [PATCH v2 0/2] Add JH8100 external interrupt controller support
This patchset adds external interrupt controller driver for the StarFive
JH81000 SoC. It can be used to handle high-level input interrupt signals.
It also send the output interrupt signal to RISC-V PLIC.
changes since v1:
- Rebased on tag v6.8-rc1.
- Dropped store reset_contorl.
- Replaced "of_reset_control_get_by_index" with of_reset_control_get_exclusive
- Printed the error code via %pe
v1: https://lore.kernel.org/all/20240111023201.6187-1-changhuang.liang@starfivetech.com/
Changhuang Liang (2):
dt-bindings: interrupt-controller: Add starfive,jh8100-intc
irqchip: Add StarFive external interrupt controller
.../starfive,jh8100-intc.yaml | 61 ++++++
MAINTAINERS | 6 +
drivers/irqchip/Kconfig | 11 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-starfive-jh8100-intc.c | 180 ++++++++++++++++++
5 files changed, 259 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
create mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c
--
2.25.1
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