lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <yfnvs3l5t7ggvdj2ebrwg7zmrn3r3su3t2xbvcfkwhb2q4sajv@ya3urqlwpzt7>
Date: Tue, 30 Jan 2024 13:00:53 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Mrinmay Sarkar <quic_msarkar@...cinc.com>
Cc: vkoul@...nel.org, jingoohan1@...il.com, conor+dt@...nel.org, 
	konrad.dybcio@...aro.org, manivannan.sadhasivam@...aro.org, robh+dt@...nel.org, 
	quic_shazhuss@...cinc.com, quic_nitegupt@...cinc.com, quic_ramkri@...cinc.com, 
	quic_nayiluri@...cinc.com, dmitry.baryshkov@...aro.org, quic_krichai@...cinc.com, 
	quic_vbadigan@...cinc.com, quic_parass@...cinc.com, quic_schintav@...cinc.com, 
	quic_shijjose@...cinc.com, Gustavo Pimentel <gustavo.pimentel@...opsys.com>, 
	Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof WilczyƄski <kw@...ux.com>, 
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
	Kishon Vijay Abraham I <kishon@...nel.org>, dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org, mhi@...ts.linux.dev
Subject: Re: [PATCH v1 0/6] Add Change to integrate HDMA with dwc ep driver

Hi Mrinmay

On Fri, Jan 19, 2024 at 06:30:16PM +0530, Mrinmay Sarkar wrote:
> Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver.
> Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the
> unrolled mapping format. This patch series is to integrate HDMA with
> dwc ep driver.
> 
> Add change to provide a valid base address of the CSRs from the
> platform driver and also provides read/write channels count from
> platform driver since there is no standard way to auto detect the
> number of available read/write channels in a platform and set the
> mapping format in platform driver for HDMA.
> 
> This series passes 'struct dw_edma_chip' to irq_vector() as it needs
> to access that particular structure and fix to get the eDMA/HDMA
> max channel count. Also move the HDMA max channel definition to edma.h
> to maintain uniformity with eDMA.

Thanks for the patchset. I'll have a look at it later on this
week or early on the next one. If you wish you can resubmit it by then
with the Dmitry' and Mani' notes fixed.

-Serge(y)

> 
> Dependency
> ----------
> Depends on:
> https://lore.kernel.org/dmaengine/20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com/
> https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/
> 
> Manivannan Sadhasivam (4):
>   dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector()
>   dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max
>     channel count
>   PCI: dwc: Add HDMA support
>   dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h
> 
> Mrinmay Sarkar (2):
>   PCI: qcom-ep: Provide number of read/write channel for HDMA
>   PCI: epf-mhi: Add flag to enable HDMA for SA8775P
> 
>  drivers/dma/dw-edma/dw-edma-core.c           | 29 ++++++++++---
>  drivers/dma/dw-edma/dw-edma-pcie.c           |  4 +-
>  drivers/dma/dw-edma/dw-hdma-v0-core.c        |  4 +-
>  drivers/dma/dw-edma/dw-hdma-v0-regs.h        |  3 +-
>  drivers/pci/controller/dwc/pcie-designware.c | 63 ++++++++++++++++++++++------
>  drivers/pci/controller/dwc/pcie-qcom-ep.c    | 19 ++++++++-
>  drivers/pci/endpoint/functions/pci-epf-mhi.c |  1 +
>  include/linux/dma/edma.h                     | 18 +++++++-
>  8 files changed, 115 insertions(+), 26 deletions(-)
> 
> -- 
> 2.7.4
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ