linux-kernel - Re: [PATCH v6 4/4] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC

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Message-ID:
 <MA0P287MB282206D6A401C372384B73DCFE7C2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
Date: Wed, 31 Jan 2024 11:46:54 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Inochi Amaoto <inochiama@...look.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Chao Wei <chao.wei@...hgo.com>,
 Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>
Cc: Jisheng Zhang <jszhang@...nel.org>, Liu Gui <kenneth.liu@...hgo.com>,
 Jingbao Qiu <qiujingbao.dlmu@...il.com>, dlan@...too.org,
 linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v6 4/4] riscv: dts: sophgo: add uart clock for Sophgo
 CV1800 series SoC


On 2024/1/14 12:17, Inochi Amaoto wrote:
> Add missing clocks of uart node for CV1800B and CV1812H.
>
> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
Reviewed-by: Chen Wang <unicorn_wang@...look.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 +++++++++++-----
>   1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 6ea1b2784db9..7c88cbe8e91d 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -5,6 +5,7 @@
>    */
>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/sophgo,cv1800.h>
>
>   / {
>   	#address-cells = <1>;
> @@ -135,7 +136,8 @@ uart0: serial@...0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04140000 0x100>;
>   			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -145,7 +147,8 @@ uart1: serial@...0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04150000 0x100>;
>   			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -155,7 +158,8 @@ uart2: serial@...0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04160000 0x100>;
>   			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -165,7 +169,8 @@ uart3: serial@...0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04170000 0x100>;
>   			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -175,7 +180,8 @@ uart4: serial@...0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x041c0000 0x100>;
>   			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> --
> 2.43.0
>