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Message-Id: <20240131102930.1841901-1-claudiu.beznea.uj@bp.renesas.com>
Date: Wed, 31 Jan 2024 12:29:28 +0200
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be,
	mturquette@...libre.com,
	sboyd@...nel.org
Cc: linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	claudiu.beznea@...on.dev,
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH 0/2] clk: renesas: r9a08g04{3,4}: Fix typos

From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Hi,

Series addresses few typos identified in r9a08g04{3,4} clock drivers.

Thank you,
Claudiu Beznea

Claudiu Beznea (2):
  clk: renesas: r9a08g04{3,4}: Use SEL_SDHI1_STS status configuration
    for SD1 mux
  clk: renesas: r9a07g04{3,4}: Fix typo for sel_shdi variable

 drivers/clk/renesas/r9a07g043-cpg.c | 6 +++---
 drivers/clk/renesas/r9a07g044-cpg.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

-- 
2.39.2


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