| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAA8EJppDQAdnceYhL_=Di0n5j3W0F2+7ntpNMxpXBXgnYoh_uQ@mail.gmail.com>
Date: Wed, 31 Jan 2024 14:25:54 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Chukun Pan <amadeus@....edu.cn>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Rob Herring <robh+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 1/3] arm64: dts: qcom: ipq6018: separate CPU OPP tables
On Wed, 31 Jan 2024 at 12:22, Chukun Pan <amadeus@....edu.cn> wrote:
>
> Some IPQ6000 SoCs do not come with PMIC (MP5496) chip,
> which causes cpufreq to be unavailable due to lack of
> cpu-supply. Separate CPU OPP tables from soc.dtsi to
> support versions with and without PMIC chip.
I went on and checked ipq6018.dtsi. It will need to be reworked before
we can continue with PMIC-less devices.
Obviously, the PMIC is not a part of the SoC. So please move the
"qcom,rpm-mp5496-regulators" node to the board files together with the
cpu-supply properties that reference that regulator.
The SoC itself supports all listed frequencies, so it is incorrect to
split the opp tables from the ipq6018.dtsi. Instead please patch the
PMIC-less boards in the following way:
#include "ipq6018.dtsi"
&cpu_opp_table {
/* the board doesn't have a PMIC, disable CPU frequencies which
require higher voltages */
/delete-node/ opp-1320000000;
/delete-node/ opp-1440000000;
};
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
> ---
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 +
> arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi | 74 ++++++++++++++++++++
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 56 ---------------
> 3 files changed, 75 insertions(+), 56 deletions(-)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> index f5f4827c0e17..06dfc2cb6b7f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "ipq6018.dtsi"
> +#include "ipq6018-opp.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi
> new file mode 100644
> index 000000000000..9c0bed2d8bf5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * IPQ60xx with PMIC (MP5496) CPU OPP tables
> + */
> +
> +/ {
> + cpu_opp_table: opp-table-cpu {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&cpu_speed_bin>;
> + opp-shared;
> +
> + opp-864000000 {
> + opp-hz = /bits/ 64 <864000000>;
> + opp-microvolt = <725000>;
> + opp-supported-hw = <0xf>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <787500>;
> + opp-supported-hw = <0xf>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1320000000 {
> + opp-hz = /bits/ 64 <1320000000>;
> + opp-microvolt = <862500>;
> + opp-supported-hw = <0x3>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <925000>;
> + opp-supported-hw = <0x3>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1608000000 {
> + opp-hz = /bits/ 64 <1608000000>;
> + opp-microvolt = <987500>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1062500>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +};
> +
> +&CPU0 {
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU1 {
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU2 {
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU3 {
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq6018_s2>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 5e1277fea725..ea72fd5739ac 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -41,8 +41,6 @@ CPU0: cpu@0 {
> next-level-cache = <&L2_0>;
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> - operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> };
>
> CPU1: cpu@1 {
> @@ -53,8 +51,6 @@ CPU1: cpu@1 {
> next-level-cache = <&L2_0>;
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> - operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> };
>
> CPU2: cpu@2 {
> @@ -65,8 +61,6 @@ CPU2: cpu@2 {
> next-level-cache = <&L2_0>;
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> - operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> };
>
> CPU3: cpu@3 {
> @@ -77,8 +71,6 @@ CPU3: cpu@3 {
> next-level-cache = <&L2_0>;
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> - operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> };
>
> L2_0: l2-cache {
> @@ -95,54 +87,6 @@ scm {
> };
> };
>
> - cpu_opp_table: opp-table-cpu {
> - compatible = "operating-points-v2-kryo-cpu";
> - nvmem-cells = <&cpu_speed_bin>;
> - opp-shared;
> -
> - opp-864000000 {
> - opp-hz = /bits/ 64 <864000000>;
> - opp-microvolt = <725000>;
> - opp-supported-hw = <0xf>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1056000000 {
> - opp-hz = /bits/ 64 <1056000000>;
> - opp-microvolt = <787500>;
> - opp-supported-hw = <0xf>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1320000000 {
> - opp-hz = /bits/ 64 <1320000000>;
> - opp-microvolt = <862500>;
> - opp-supported-hw = <0x3>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1440000000 {
> - opp-hz = /bits/ 64 <1440000000>;
> - opp-microvolt = <925000>;
> - opp-supported-hw = <0x3>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1608000000 {
> - opp-hz = /bits/ 64 <1608000000>;
> - opp-microvolt = <987500>;
> - opp-supported-hw = <0x1>;
> - clock-latency-ns = <200000>;
> - };
> -
> - opp-1800000000 {
> - opp-hz = /bits/ 64 <1800000000>;
> - opp-microvolt = <1062500>;
> - opp-supported-hw = <0x1>;
> - clock-latency-ns = <200000>;
> - };
> - };
> -
> pmuv8: pmu {
> compatible = "arm,cortex-a53-pmu";
> interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists